Square Wave Generator - Max Frequency?

[bones349]

Hey All,

I'm using the Square Wave Generator.vi function in my FPGA code.  Using LV 8.5, NI 7831-R FPGA board.  Is there a limit on the max frequency?

I did a test today, and saw the signal start to display some 'jitter' at around 40 KHz and above.  The rise time on the Square is also very 'ugly' at these higher frequencies.  The signal is looking very much like a Shark Tooth.

I'm using the function inside of a Single Cycle Timed loop, and my clock is just the default 40 MHz.  My application needs to be able to output an analog signal up to around 100-120 KHz (0 - 8V swing).  No, I did not have any load hooked up while I was scoping.

I scoped the signal at the Screw Terminal of the SCB-68 breakout box, if this makes any difference?  The spec sheet for the NI-7831R says it supports up to 1MHz "update rate", not sure what exactly this means.

[Robbob]

Bones,

You should be able to go much faster than 40khz and still maintain signal integrity.

According to the User Manual,

Minimum pulse width
Input ............................................25 ns
Output .........................................12.5 ns

Although with many devices such as the sbRIO we only clock up to 10Mhz to maintain integrety. I would assume the FPGA boards would be similar.

I would verify your connections and make sure they are all tight. Also, which scope are you using? Have you tried putting a large load in series with the connections? Can you post a screenshot of the code you are using to develop the signal?

Message Edited by Robbob on 10-08-2009 04:27 PM

[Spex]

Hi Bones,

Sounds like you are using the analog output of your 7831R to generate a square wave (0-8V) not a digital output, correct?

If so, then the specs you are interested in from the Analog Output section of the 7831R user manual are:

Update time ............................................ 1.0 μs
Max update rate...................................... 1 MS/s

Slew rate .................................................10 V/μs

Given those stats, you can see that the analog output I/O nodes can only operate at 1MS/s, not at the 40MHz loop rate you are attempting in the Single-Cycle Timed Loop (SCTL).  You need to pull your square wave generation code out of an SCTL and into a while loop timed at 1MHz (40 ticks timer).

Regarding the edges of your square wave, based on the slew rate of 10V/us, I would expect a rising edge of about .8us with another 3-4 microseconds of settling time for the value to settle within 16 LSBs of the 8V.  

Regarding the overall quality of your square wave output, you will get about 9-10 updates per square wave period at 100kHz.  The first microsecond of each transition (about 1/5th of the up or down portion of the wave) will be slew rate limited and rising at 10V/us.

I can't say if that is good enough or not for you, but if you are still having issues, or the output doesn't match my theoretical description, feel free to post your code and screen shots of your scope capture so we can help you debug further.

Cheers,

[bones349]

Hi Spex and Robbob,

Yes, the output in question is one of the 8 Analog Outputs on the 7831R.  Im using Analog because I switch between different functions to drive my device.

I will try Spex's advice, and take the Square Wave generator out of a SCTL.  I understand that I can only update the analog I/O nodes 1MS/s. 

I don't understand why I can't keep the Square Wave with the 40 MHz clock though?

I mean, if I send a signal that is being updated at 40MHz, to a DtoA that can only update at 1MHz, wouldnt 1 in 40 data points be plotted?  This is fine if my signal has a max frequency of less than 1MHz?

I've attached my FPGA code too.  The Square Wave generator is found in Case #2,4.

Thanks!

[srm@viewpointusa.com]

The fundamental issue with your VI and it's ability to run the way you expect it to, is that the rate of this loop is much slower than you think it is.  If you add a delta tick timer display to your loop, you will probably find that is runs significantly less than 200 kHz.  Since your loop includes both AI and AO, you will limited to the AI rate of ~200 kHz.  Since you have not pipelined any operations, the rate will be much less.

The jitter is due to this lower rate which will become more apparent when you are trying to generate higher freq waveform.  I believe you are seeing the correct rise time but the edge jitter has a granularity of ~7 us.

If you create  a test case with ONLY the square wave generator to feedback node to analog output, it should run a 1MHz (40 ticks) as expected.

In your case 4, you are sending the square wave into a PID with the analog input.  in this case, your loop rate will still be limited to the AI rate of ~200 kHz.  if you try to output a 40 kHz square wave with only 200 kHz update rate, it will not look too good either.

No sure if this helps but it is an explanation of what you are seeing.

Message Edited by stu@viewpointusa.com on 10-09-2009 03:48 PM

[bones349]

Thanks Stu,

I did a test, and noted that my code is actually running around 120K-130KHz.  I understand now why the Square Wave is looking the way it does.  I may be able to just use a bench top signal Generator for my tests that require higher frequencies.

I notice the 'bigger' FPGA boards sample inputs at a faster rate (750KS/s), that may also be an option.

[srm@viewpointusa.com]

You can implement the analog output in a separate loop and achive the 1 MHz rate for just the AO.  Your PID loop will still be limited to the AI loop rate.  This rate can also be sped up with FPGA optimization methods.

Newer boads can be faster as well, as you noted.