Synchronization between a loop in the FPGA and a loop in the processor

[Alvaro10]

Hi!

Im programming my CRIO using two loops(with frequency of 1KHz), one is in the FPGA and the other is in the proccesor, I would like to have both starting at the same moment, but I can´t synchronize correclty them.

For be sure that both are synchronized I use a boolean variable that switch on or off every time that the loops execute, after I read these variable in the digital output of my CRIO, the problem is that the variable that corresponds to the loop in the FPGA is fixed but the variable that corresponds to the loop in the procesor is always moving, so these booleans variables are sometimes synchronized an sometimes not.

Maybe this is not the rigth way for comprobe if two parallel loops are synchronized, it is?

If is the rigth way for comprobe if both loops are starting at the same moment, how could I synchronize them?

I also attacht the VI in the FPGA and the VI in the procesor.

Thanks a lot!

Regards!

[JonasM]

Hi Alvaro10,

There is a Community post that does syncronize the RT time with FPGA Time, maybe this can help you on the way to synchronize both VI's.

https://decibel.ni.com/content/docs/DOC-23156

FPGA Timekeeper 1.1b0\examples\Synchronize to RT - cRIO was the example I looked at.

[JonasM]

Hi Alvaro10,

There is an other way to synchronize the loops as well. You can use Interrupt on FPGA and Invoke methods on the RT VI to synchronize them. I've attached two images that will show you how this is done.

RT VI

You will find the Invoke methods under FPGA interface on the functions palette.

FPGA VI

You will find the Interrupt function under Synchronization palette on the FPGA.

This way the FPGA will firstly send an interrupt to RT VI and by using wait on IRQ the RT loop will wait for the interrupt and by using acknowledge IRQ the FPGA VI will wait for this to occure before running if Wait until cleared input is wired true on Interrupt VI as shown above.