12-13-2013 08:41 AM
Hello.
We are using CompactRIO to perform vibration and counter measurements. We are using DSA modules (9234, 9229) for analog signals and 9411 modules as digital input for counter period measurement. We need to perform these measurements in sync over a period of 24 hours.
DSA modules use the internal 13.xx MHz of one of them as master, while counter measurements use the FPGA 40MHz clock. The problem is that after a couple of minutes we see a noticeable drift between them.
Two questions:
1. Is it possible to derive a 13.xx MHz clock from the FPGA 40 MHz clock, and use it as a master for DSA modules?
2. Is it possible to export the DSA master 13.xx MHz clock and use it as an input to the FPGA? This way we could quantify the drift between both clocks.
We found this post: http://forums.ni.com/t5/LabVIEW/Export-FPGA-Onboard-clock-to-io-modules/td-p/1149080, but it's not exactly the same situation.
Kind regards,
Daniel Ramírez
CLD - CADETECH S.A.
Chile
12-14-2013 10:21 AM
Yes - there is a method of calculating speed on the FPGA and with reference to the oversample clock. Consider this document:
http://www.ni.com/example/31301/en/
It uses a high speed analog, yet it time stamps level detection - a digital output - to the DSA oversample clock.
Then in the LabVIEW Sound and Vibration Measurement Suite Order Analysis tools, you can find the digital tachometer VI used to prepare the speed pulses for resampling and order analysis.
Let us know how this works.
12-16-2013 06:31 AM
Thanks for your answer, Preston. We are not doing order analysis with this, but basically we face the same clock drift problem.
I see from the reference you sent that it is possible to measure the DSA timebase using the 40MHz clock (our question number 2), so that's good news in case we can't use a FPGA derived clock as DSA timebase (question number 1).
Kind regards,
Daniel R.