Hello everyone,
I've written code to make pulses and used them to modulate a sine wave using a sine waveform generator. I generate the pulses in a Single Cycle Time Loop and do the modulation with the sine wave in a simple While loop. I'm using myRIO FPGA, and its analog output can't be used in the Single Cycle Time Loop, so I use it in the While loop. Both FPGA FIFOs are used in the Single Cycle Time Loop. However, when I read back the data on the host, I find that the pulse and modulated sine wave aren't in phase with each other; there's some delay.
If anyone has experience with this issue, I'd appreciate your assistance. Please check out the screenshot of the modulated sine and pulse waveforms below.
Thanks and regards.
