TCP Read Funcition-CRLF Mode,FPGA

[Quan0621023]

Because the number of bytes is different, I want to use CRLF mode.

How does FPGA send CRLF to TCP Read Function?

[Terry_ALE]

Which FPGA card are you using?

The code below cannot run in LabVIEW FPGA.  These are LabVIEW for Desktop (software, not FPGA) functions.

LabVIEW FPGA does not have string data type.  Strings are represented by their ASCII code equivalent.

[Quan0621023]

Thanks Terry_ALE.

I am using Altera DE2-115 (Cyclone EP4CE115 FPGA) + WIZnet w5500.

Is there any other method for labview?

[Terry_ALE]

LabVIEW has an add-on called LabVIEW FPGA.  Do you wish to run TCP messages on an FPGA?

The board you have cannot be programmed using LabVIEW FPGA.

[rolfk · Accepted solution]

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@Quan0621023 wrote:

Thanks Terry_ALE.

I am using Altera DE2-115 (Cyclone EP4CE115 FPGA) + WIZnet w5500.

Is there any other method for labview?

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As already mentioned, LabVIEW FPGA does not work for this board. The Xilinx toolchain used in the FPGA toolkit not surprisingly only works for Xilinx chips and is both technically and legally limited to be used for NI FPGA targets.

That doesn't mean that you could not program your Altera device in VHDL or similar with your favorite FPGA programming toolchain, which most likely will be Intel's Quartus® Prime software.

Now, TCP/IP is simply a byte stream oriented protocol and every basic data element is a byte. And strings are typically represented in ASCII codes, which are simply according numeric byte values. So you would simply place the according byte values (0x0D 0x0A for <CR><LF>) on the wire. Now, programming variable sized messages in FPGA is not a trivial task and especially handling the receiving side in FPGA will very quickly give you a monster of logic circuit that will clobber up FPGA fabric faster than you can say "Huu?", so you may reconsider about trying to do variable sized messages in FPGA logic.

Also while there are FPGA IP cores to handle Ethernet interfaces directly in fabric and connect to them from other FPGA components, the typical approach here is that the Ethernet interface on most boards only uses some peripheral FPGA fabric to connect to the data bus and the rest is handled by the OS on that board. So the actual TCP/IP stack implementation is not on FPGA but rather in the OS that runs on such a board and accordingly you do not program the network communication directly in the FPGA but rather in software that runs in that OS. Fully in FPGA implemented TCP/IP stacks are pretty rare, rather specialized and very expensive IP cores for specialistic high speed IP network infrastructure.