TDMS Data neither saved nor displayed[ Edited ]

[Ihab]

Hello

Please find  attached my project  FPGA vi and RT Vi

I am applying the following tutorial

http://www.ni.com/tutorial/11198/en/ 

I need to log the data on file and display it inthe same time

Somthing went wrong  with snippet 

Please check my VIs below.

And send me any help

Thanks

[RavensFan]

Your channel names array is empty going into the TDMS write.  I suspect that is the problem.

Are you sure you are getting data into the RT VI?  Put an indicator or probe in there to be sure the data is coming through.

[Ihab]

Hello RavensFan

Thank you for your reply.

yes you right 

I modified my channel names

and I added an indicator to the data going ut from FIFO-READ

I hope that this is the right place to put the indicator you mean.

But it did not bring any data.

Which means there is anoher poit in the code.

Many Thanks in advance  

[RavensFan]

The next question is are you sure your FPGA code is running?  If you start it from the front panel window, do you see it executing?

Put indicators on your loop iteration terminals "i" and  see if they keep incrementing.

You have a FIFO.Start node on your real-time code which is interesting to me.  It makes sense that it would be there.  But I'm looking at a project of mine where I used 3 FIFO's, and none of them use that node.

Another thing.  You have a Feedback node in there that checks for the FIFO to timeout and sets the "Overflow" indicator.  But you initialize that with a True constant, so the result of the OR will be true right away.  And you RT code will stop after one iteration.

[Ihab]

Hello RavenFan

Thank you fro yur reply

Re: TDMS Data neither saved nor displayed[ Edited ]

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‎05-29-2016 01:07 PM - edited ‎05-29-2016 01:34 PM

The next question is are you sure your FPGA code is running?  If you start it from the front panel window, do you see it executing?

Put indicators on your loop iteration terminals "i" and  see if they keep incrementing.

I put an indicator it was incremanting  but till 3 or 4 and reset again , I still do not why??? 

You have a FIFO.Start node on your real-time code which is interesting to me.  It makes sense that it would be there.  But I'm looking at a project of mine where I used 3 FIFO's, and none of them use that node.

By the way , I am following here the Getting Started  Tutorial   http://www.ni.com/tutorial/11198/en/ 

Another thing.  You have a Feedback node in there that checks for the FIFO to timeout and sets the "Overflow" indicator.  But you initialize that with a True constant, so the result of the OR will be true right away.  And you RT code will stop after one iteration.

I changed this to initializ to F, still neither displaying nor saving 

Plase do you have anther hint?

[Ihab]

The next question is are you sure your FPGA code is running?  If you start it from the front panel window, do you see it executing?

Put indicators on your loop iteration terminals "i" and  see if they keep incrementing.

I put an indicator it was incremanting  but till 3 or 4 and reset again , I still do not why??? 

You have a FIFO.Start node on your real-time code which is interesting to me.  It makes sense that it would be there.  But I'm looking at a project of mine where I used 3 FIFO's, and none of them use that node.

By the way , I am following here the Getting Started  Tutorial   http://www.ni.com/tutorial/11198/en/ 

Another thing.  You have a Feedback node in there that checks for the FIFO to timeout and sets the "Overflow" indicator.  But you initialize that with a True constant, so the result of the OR will be true right away.  And you RT code will stop after one iteration.

I changed this to initializ to F, still neither displaying nor saving 

Plase do you have anther hint?

[RavensFan]

I have no idea why your FPGA code would be starting.  Your inner For Loop should go 0 through 3.  But the outer while loop i should be conitnually getting larger.

If your FPGA is resetting and restarting, then I suspect a much larger problem.