Transfer 1-d array using DMA FIFO from FPGA

[ecksor]

I am trying to transfer a 1-D array of two U32, using a U32 configured FIFO to the host,

but I get error due to connecting to different terminal types,

It looks very simple, I've found many samples around here with very similar treatment, but I can't see the problem?!

[dan_u]

The data type of an FPGA FIFO can't be an array, it must be scalar. In your case it's a U32.

And you can only write one element to a FIFO per Write operation. So you'll have to write the data to the FIFO element by element.

[ecksor]

But in this example:

https://decibel.ni.com/content/docs/DOC-6303

I think FIFO is passing an array, right?

[dan_u · Accepted solution]

There's a for loop indexing the array... So the write operation is element by element.

The read operation (on the host) can read several elements at a time (--> an array).

[ecksor]

Thanks,

[ecksor]

Thanks for your response.

But it leads to another question,

How can I transfer several channels in this situation on a Single-Cycle Timed Loop?

I am using Timed Loop because I need to read digital data at high speed up to 40MHz, and because of limits in number of DMAs I need to pass several channels by one FIFO.

[dan_u]

It's quite simple: send one channel per iteration. If you need the sampling of all channels to be synchronous you'll have to store the values in a shift register to send it later.

In the screenshot you posted you could change the code like this (looks like you're using counter values from 1-32):

- when the counter reaches 32, write the data of ch1 to the FIFO and store the value of ch2 into a shift register

- when the counter is at value 1 write the value of ch2 (which was stored in the shift register) to the FIFO

- in all other cases just increase the counter

[ecksor]

Thanks again, for your great help.