Trouble generating 50MHz clock digital output with myRIO-1900, sbRIO-9602, and PXI-7811R

[jtrujil1]

Hi all,

I'm trying to drive a DS92LV16 16-bit Bus LVDS Serializer/Deserializer chip using any NI FPGA I have my hands on. The problem is that this chip needs as a minimum a 50 MHz clock. My FPGA boards all have 40 MHz built-in clock, and when I use a derived 100 MHz clock to generate a 50 MHz digital output, the signal comes out weak. What is mean is the oscilloscope is showing a peak-peak amplitude of less than 1 Volt when running at 50 MHz. When I drive a 4 MHz clock through a digital I/O pin I get nice peak-peak signals around the 3.3 V needed to drive CMOS logic.

Can I use the myRIO-1900, sbRIO-9602, or PXI-7811R to do this? Can newer hardware help? If so what models would work? Or can I use a buffer chip to precondition the signal for driving hardware?

Thanks!

[jtrujil1]

Here is what the signal looks like on my oscilloscope at 8 MHz. See attached.

[jtrujil1]

And here it is again at 50MHz. Major voltage drop. Not high enough to clock the CMOS chip I'm driving at 3.3V.

[edjones93]

You've mentioned three different FPGA's. Which one is currently showing this behaviour? I wouldn't be surprised if it was the myRIO but the 7811R should be able to achieve up to at least 40Mhz, have you tried the 7811R at 40Mhz?

[jtrujil1]

I mention three systems because these are the systems i’ve tried to generate a 50 MHz clock. They all exhibit the same behavior as shown in the pictures I uploaded.