I've written a VI that reads in a signal at 2048 Hz and sends it to a SCTL to filter and calculate the FFT with size 8192.
Between the filter is a buffer in the form of a VI-defined FIFO that stores the filtered values. So once it's filled, it sends 8191 input values from the past to the FFT and then the 8192nd input value is the latest value from the input signal.
The FFT has a latency of 20534, but instead of the FFT starting to output a minimum of 20534 ticks after the first input value of the frame, it outputs only after receiving 20534 valid inputs. This means that it outputs the first frame only after receiving 8192 valid input from the first input, 8192 valid inputs of the 2nd frame and an additional 4150 valid inputs of the 3rd frame. This also means that if I only send it 8192 valid inputs (the size of the FFT), it never outputs. It just continues waiting for the additional valid inputs.
Can any one help me with this? Included is my VI as well as a image explaining the timing.
