Typedef FPGA VI Reference Does Not Retain Interface Definition

[User002]

There seem to be a bug with the when typedefing a FPGA VI reference and importing an interface from a bitfile.

Steps to reproduce:

Have a previously typedef'ed FPGA reference inside a cluster as a member variable in a class.

- Configure the FPGA Ref typedef

- Import a a new Interface from a bitfile

- Apply the changed FPGA reference typedef onto the class

- Save all.

- Close the class, alternatively restart LabVIEW

- Start LabVIEW, open the FPGA Reference typedef.

- Possible bug is that the typedef refers to the old interface for some reason?

Br,

/Roger

[nathand]

Wherever you have an Open FPGA VI Reference, do you have the option checked to bind the host FPGA reference to that type definition?  Somewhat confusingly, it is the Open FPGA VI Reference that configures that type definition, not the other way around.  If you bind the Open FPGA VI Reference to a type definition, update the interface in the Configure Open FPGA VI Reference dialog, and don't touch the type definition.

[User002]

---

@nathand wrote:

Wherever you have an Open FPGA VI Reference, do you have the option checked to bind the host FPGA reference to that type definition?  Somewhat confusingly, it is the Open FPGA VI Reference that configures that type definition, not the other way around.  If you bind the Open FPGA VI Reference to a type definition, update the interface in the Configure Open FPGA VI Reference dialog, and don't touch the type definition.

---

I guess my problem is if I configure the typedef'd FPGA VI Reference with another FPGA interface (FPGA VI front panel + FIFOS) to be of another type and save, it should _not_ revert stuff back to the interface that was before? If it would be the expected behavior, why have it changeable in the first place?

See image above on how I open the FPGA Ref's.

Br,

/Roger