Uncontrolled registers in Four-wire Register with Cache in DRAM FIFO v2 FPGA.lvclass

[UMASO]

Hello, there are registers placed inside four-wire register with cached VI in Process.vi of DRAM FIFO v2 FPGA.lvclass.  

I guess these registers could be just removed.  Would NI be aware of this and modify for next version of DRAM FIFO?

[Intaris]

What is the source of the boolean connected to the "Enable?" terminal of the shift register?

Just removing the register will have two effects on the code, latency of that path is reduced by one meaning there may be a latency imbalance between different paths and also the data on the output will periodically have invalid values.

[UMASO]

There are three pairs of registers (data and enable).  The first pair is input register and the second pair is for caching, when "ready for output" goes down.  These two pairs are controlled by state machine placed top-right of the block diagram.  However, the third pair is out of the control by the state machine.