Using LabVIEW, how do I create VHDL or Verilog IP for use in Vivado

[AnthonV]

I completed a project targeting a cRIO for a client.  However they want to incorporate the IP in their own Xilinx Vivado project so they are asking me to recode my solution in Simulink to target a Xilinx Zynq.  I would prefer to keep Simulink out of the loop and rather use my LabVIEW code as-is and compile to VHDL or Verilog.  Is there ANY way to do this?

Any help would be appreciated.

[Mike.B]

Hi AnthonV,

If I read your post correctly, you're essentially wanting to "port" your code from LabVIEW FPGA to Vivado, in which case you'd want to follow the below documentation.

Exporting FPGA VIs as Vivado Design Suite Projects (FPGA Module)

[AnthonV]

Thanks for the lead Mike, I will try this on the weekend and report back on whether it is a solution.  Sounds like it could be exactly what I want.

[Jacobson-ni]

Be aware of the first note that mentions not all FPGA targets support this behavior. I also want to point out that this feature is only available from LabVIEW 2017 onward (relatively new feature).

[AnthonV]

Thanks for the head's up, I would have struggled with my 2016 this weekend, I'll upgrade first.  

Just a question - at any point in the process would I actually see an IP block or a vhdl file that is the equivalent of my vi?  So I would want to take my existing vivado project and drop myfunc.vi into it (right click>add IP>myfunc in Vivado Block Design).

[Jacobson-ni]

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@AnthonV Just a question - at any point in the process would I actually see an IP block or a vhdl file that is the equivalent of my vi?  So I would want to take my existing vivado project and drop myfunc.vi into it (right click>add IP>myfunc in Vivado Block Design).

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I've used this feature very rarely for debugging so I'm not really sure to be honest.