Verilog, edn, edf and VHDL files in LabVIEW

[303032]

Hi,

I am trying to import  some hdl files in LabVIEW through IP Integration Node.

When I give it pure VHDL files(with no Verilog instance) only then it works and generates the respective icon in my block diagram. 

When I try to give it edf or edn (netlist files) or some VHDL top module with Verilog sub module then it doesn't take it as input. 

I have 2 questions:

Why it doesn't accept edn or edf files as legal input? Am I making some mistake?

What if some of the sub modules are written in Verilog, what will we do then? How will we import our modules in the LabVIEW in that case?

Please note that I am using LabVIEW version 2018.2.

Best and warm regards

Xing Wo

[303032]

Hi,

My problem seems to be quite unique :). I have two problems.

I added a VHDL file into IP integration node. Worked fine till the end.

But then I tried a Verilog module, that was wrapped around by a VHDL wrapper. Compiler complained that it can't find the Verilog module(I also added that file as well).

Secondly, I tried to add *.edn file, which I generated through Vivado earlier using the same VHDL wrapped Verilog file. Again,  its not recognizing this file. And is not letting me to proceed. 

What may be the way around?

Regards and thanks

Tahir

[303032]

Hi, 

Is there any way that I can generated XML file from VHDL files directly. 

Seriously guys, its very cumbersome to write these files again, all the way after writing VHDLs.

So please, let me know if any body knows.

Regards

Tahir

[GerdW]

Hi Tahir and Xing Wo,

please keep related discussions in one thread…

[David-A]

Theres a CLIP wizard that will generate the xml for you. I always use that to generate the initial xml file and then manually modify from there. 

http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgaconcepts/fpga_clip_using_wizard/

[303032]

Hi,

If I have edn or edf files only, it doesnt let me proceed. Actually I have a VHDL top module and all sub-modules are in Verilog. So, I generated edn and then edf files to create a component through both(CLIP and IP Integration Node) for use in LabVIEW VIs. So, can you put some light in this case. Actually all other sources are are mentioning netlist files, but it seems that neither CLIP nor IP Integration node accepts netlist files. Please put some light if possible. Actually I am a Verilog programmer 😞

---

@David-A wrote:

Theres a CLIP wizard that will generate the xml for you. I always use that to generate the initial xml file and then manually modify from there. 

http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgaconcepts/fpga_clip_using_wizard/

---

[303032]

---

@GerdW wrote:

Hi Tahir and Xing Wo,

please keep related discussions in one thread…

---

You combined two totally different questions in one thread. 

[David-A]

CLIP and IPIN support various netlist types. The edn and edf file types are supported. 

http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgaconcepts/integrating_hdl/

With regards to pulling in verilog, it sounds like you're doing things correctly. Compile your verilog into a netlist, then create a vhdl wrapper for it. Can you confirm that you're able to create even a simple CLIP using just vhd files? The CLIP adder project is a good basic example that you can build upon to see what it is about your netlist files that the wizard doesn't like. 

Access the CLIP adder project by opening the example finder and navigating to Hardware Input and Output>>FlexRIO>>FPGA Fundamentals>>User CLIP>>CLIP Adder.

[303032]

---

@David-A wrote:

CLIP and IPIN support various netlist types. The edn and edf file types are supported. 

http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgaconcepts/integrating_hdl/

With regards to pulling in verilog, it sounds like you're doing things correctly. Compile your verilog into a netlist, then create a vhdl wrapper for it. Can you confirm that you're able to create even a simple CLIP using just vhd files? The CLIP adder project is a good basic example that you can build upon to see what it is about your netlist files that the wizard doesn't like. 

Access the CLIP adder project by opening the example finder and navigating to Hardware Input and Output>>FlexRIO>>FPGA Fundamentals>>User CLIP>>CLIP Adder.

---

You are correct sir. 

I am using IP integration node. 

NI guys claim that edn or edf files are accepted, and this is not yet proven(at least not for IP integration node). VHDL files function, and this is proven. IP integration node doesn't accept edn or edf files.

CLIP does accept edn and edf files. Worst part come's when you place your such generated components in VI and they don't function, it some time make you jump out of the window.

I don't think it will take huge effort to NI guys to add Verilog support in their modules(a direct HDL code support like VHDL), neither it will make them look cheap. 

By not doing it, they are certainly losing a huge market segment. Not everybody in this world is a LabVIEW guy, some guys are like me, the HDL guys.

Thanks cheers and wishes for a happy progressive day

Tahir

[Terry_ALE]

Have you tried using Vivado Export?

http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgahelp/export_fpga_vis_howto/