Hello LabVIEW community,
I am currently working on developing a distributable version of my FPGA code in LabVIEW. I have implemented and tested the logic on LabVIEW FPGA successfully, and now I'm in the process of creating an IP (Intellectual Property) of the subVIs using the IP Integration Node provided by LabVIEW FPGA.
To organize the IP components and make them easier to manage, I decided to consolidate all the IPs into a single subVI by placing them inside a Single-Cycle Timed Loop (SCTL). The individual IPs work flawlessly when placed directly inside the main VI and SCTL. However, when I attempt to create a consolidated IP by combining all the IPs within the SCTL inside a SubVI, I encounter a Vivado Error during the netlist generation process.
I would greatly appreciate any guidance, insights, or suggestions from the LabVIEW community regarding this Vivado Error during the netlist generation for the consolidated IP.
Thank you in advance for your time and assistance. I look forward to hearing your thoughts and experiences on this matter.
Best regards,
Hussain Ali
