What does "mark as probe sampling source" do?

[Ben]

I noticed a while loop used the State Machine project had a right click option "mark as probe sampling source" so I clicke dit and it brought up a proble watch window and then I ran the example.

What is that thing supposed to do and when would I use that option?

I imagine I could find the answer myself but while I a searching, does any one know?

Ben

[AnalogKid2DigitalMan]

Ben:

Here is link to the Help (not that I read or understand it):

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgahelp/using_sampling_probe/

-AK2DM

[Ben]

Thank you AK2DM !

I could have used that two days ago... sorta.

I was trying to enhance  VI that was a State Machine that did not have a flow diagram to go with it and the transision were let's say "convoluted" where the next state depended on something that happened about 5 states ago.

I resorted to watching in light-bulb mode and end up with 3 pages of hand written notes documenting the states.

Reading the help you found it seems the first step is to mark the loop as a probe sampling source.

Then go to the enum wire feeding the SR on the right side of the structure and right-click and choose Sampling Probe >>> While Loop.

When the State machine runs the numeric representation of the enum is shown in the Sampling Probe Watch Window.

I played a little with exporting the graph to clipboard and trying to decypher in the hopes I could cas the values back state names but I have not carcked that nut yet.

Thank you!

Ben

[Ben]

Cracked the nut.

After "export to clipboard" the above code will give an array of the states and the order they were executed.

In the above I disconnected the enum from the type def. the original type def is from the Simple State Machine template. The above could be adapted to other state machines by replacing the enum with the type def that is used in the state machine.

Take care,

Ben

[Ben]

There are some short-comings in the code I shared above. But the idea is sound and can be used as a tool. If you do so, watch out for the bit order. It is not straight forward.

Ben

[Jacobson-ni]

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@AnalogKid2DigitalMan wrote:

Ben:

Here is link to the Help (not that I read or understand it):

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgahelp/using_sampling_probe/

-AK2DM

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I've used this feature for FPGA VIs before but didn't know it could be used on a host VI, very cool.