Writing multiple elements to a FPGA to RT DMA FIFO

[James_McN]

Are you able to share the host image for reading this FIFO? Or even better if you can share some code as I'm struggling to picture the flow.

No timeouts is great news and means your right it would be worth looking at the host.

So lets consider we have effective 3 channels - timestamp low, timestamp high, analog data? (whatever the 3rd write is writing). We will call them 1,2 3. From what is shown in the code it appears they are in fact going to 1 DMA channel (The "FPGA to RT FIFO" channel). To make 3 seperate DMA channels you have to create 3 separate FIFOs in the project.

The normal way to use the interleave and decimate function is that you write one channel at a time, so the order in your FIFO is:

1,2,3,1,2,3,1,2,3,1,2,3

Then the decimate function, expanded to 3 outputs would give you 1) [1,1,1,1], 2)[2,2,2,2] 3)[3,3,3,3]

However, the way I read your code from the screenshots seems like you are writing 32 of each channel at a time so you are going:

1,1,1,1,1,1,1...(x32), 2,2,2,2,2,2,2... (x32), 3,3,3,3,3,3,3..(x32),1,1,1,1,1,1,1...(x32), 2,2,2,2,2,2,2... (x32), 3,3,3,3,3,3,3..(x32),

So the decimate function is going to get confused, roughly giving:

1) 1,1,1,1,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3

2) 1,1,1,1,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3

3) 1,1,1,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3

I don't know if this explains what you are seeing?

To be honest, I'm not sure I see the need for the writing of 32 samples at a time on the FPGA, if you ad the same code but wrote 1 at a time it may be simpler, though I don't fully understand what you need to achieve yet.

[Harss]

Hi,

Yes you are  right!!  this is what I am doing on the FPGA.

I am sorry for not being able to briefly describe my requirements in the earlier discussion. Here is what I am trying to do.

1:On the FPGA.

I need to acquire data at the rate of 1 MS/s and timestamp each sample value . I have accomplished this using the NI TIme Sync FPGA Timekeeper VI . Now what is working fine is acquiring the data at 1 MS/s and timestamping each sample value . My next job is to process this data . So the processing is like there are two user defined thresholds , namely the upper threshold and the lower threshold . So I need to check the rise time (i.e. a kind of trigger which checks if I have sample values above the lower threshold , if yes then I need to check how much time does it take , considering that the sample value is above the lower threshold . How much time it takes to reach the upper threshold or probably cross the upper threshold , in case that time is greater than or equal to 32 microseconds then yes transmit this data chunk along with each and every sample of this chunk being timestamped onto the cRIO). Now I have done the processing on the cRIO and am able to set it up correctly . So I have this chunk of valid data elements(i.e. 32 data elements ). I even have a chunk of timestamps(i.e. 32 elements).Now I have an array of 32 elements of elements and the array of 32 elements of tiestamps . I now need to transfer these values to the cRIO. My another concern is when I read these elements on the cRIO they need to be in sync i.e. For every data element I need to associate it with its respective timestamp so its important to pack them onto the same FPGA to RT DMA FIFO . So I am unable to determine a way in which I can pack them together when both of these are in the form of 1 D array . I write these elements at the same time onto the FIFO (i.e. 32 elements at a time) . I do not know how to reconstruct them onto the cRIO because decimate 1D array would not work in this case.

I have attached the snapshot of the FPGA VI and the RT VI as I do not have the actual  VI with me at the moment.

Further help/suggestions would be really appreciated.

Thanks .

[James_McN]

Ah OK that makes more sense!

I believe the issue I described above probably is the issue you are seeing then, if so then there are two solutions:

1) On the FPGA you change the way you right so you right an interleaved channel so AI(1), TimeLow(1), TimeHigh(1), AI(2), TimeLow(2), TimeHigh(2) .. to sample 32. Then your current RT will probably work better.

2) On the RT you need to break down the data differently. You are sending Segment1,Segment2,Segment3 where each segment is AIx32, TimeLow x32, TimeHigh x32 so with this format I would:

a) Reshape to 2d array which has 96 (3x32) in each row so each row is a segment/trigger whatever your term is for it.

b) Take each row and split into 3x32 which are now your channels. Now you can join your timestamps

This route may be a bit CPU intensive depending on the frequency of your triggers.

Understanding this I would also recommend restructuring your loops. I would have one loop that just reads from the AI and timestamp local FIFO, puts them into a cluster or similar together and then another local FIFO to the trigger detection loop.

The reason is, each time you see a trigger and want the data you put 96 samples into the DMA FIFO. Assuming best possible conditions each sample will take 25ns which means in total 2.4us and you will miss a couple AI samples. Because your timestamps are buffered it means these will get out of sync as well over time. I've attached a basic sketch of what I mean.

[Harss]

Hi,

Thanks a lot for your elaborate expalanation . I really appreciate it!!

I just wanted to clear my understanding below based on the discussion we had

I will definetly try the solution 2) which you mentioned because yes you are right, in case I use a FOR loop to send in each element across to the FIFO as mentioned in solution1) , it could mean loss of data in case it takes longer than 1 microseconds to write all the 32 elementsone by one. So the second option looks much promising , which means I would have to read the elements from the FIFO when the number of elements remaining equals to 96 need to flush the FIFO and the reshape to 2D array would give me (32*3)elements in one row(or incase I need to flush out more elements then the dimension of the row would vary accordingly). Now I need to use a FOR loop with autoindexing  which would give me my 1 D array say the first row, now I split this array into 3 parts (32*1) for array values , (32*1) for high timestamp and (32*1) for lower timestamp now I can merge the timestamp values and do the network Streams.

In case I need to change the FPGA VI  then

1:I should read the AI in the reading loop(second while loop) just like its done now in the snapshot, and now I also read the values from the Local buffer which stores the timestamp, do some processing in the second while loop just similar to now , but now you suggest that once I get the valid data chunk in the processing part then I need to use another Target DMA FIFO . which stores this data chunk along with the timestamp values and later introduce a Third While loop which is not there in the current snapshot which just reads each element and sends single element at a time into the FPGA to RT DMA FIFO using a FOR loop with auto indexing enabled like (AI*1),(Timestamp,High*1),(Timestamp,Low*1)....(AI*32),(Timestamp,High*32),(Timestamp,Low*32).

Could you please check if my understanding is correct based on our previous discussion.

I once again thank you for all your inputs 🙂

Thanks.

[James_McN]

Hi Harss,

I think with either solution then you should change to add the extra loop as this could always be an issue, then either issue should work

[Harss]

Hi,

I tried to implement the second solution today.

1:I kept the FPGA VI as it is

2:Changed the VI on the RT to use the Reshape Array while reading the elements fromm the FIFO

The solution allowed me to prevent channel switching.Though I could not test it exhaustively

I have attached the VI of the RT with the necessray changes being made. However, I noticed an unexplained behaviour while using Network Streams.

1:When I use the Create Network Stream Writer Endpoint function (i.e. Initialization of the Network Stream) outside the while loop. The elements remaining in the FIFO keep on increasing and the FPGA to RT FIFO Times Out.

2:When I use the Create Network Stream Writer Endpoint function(i.e. Initialization of the Network Stream) inside the While loop. The FPGA to RT FIFO does not Time Out.

I am unable to understand this behaviour and could you also please provide any hints as to how to wire the Network Stream Write Single Elements function inside the For loop so that I can write the values correctly into it.

Thanks once again.

[Harss]

Hi,

I further checked this issue and now  I am able to get the Sample values and timestamp in sync on the cRIO. I am also able to reconstruct the timestamps properly on the cRIO. The only issue is using Network Streams. The issues while using Network Streams are as follows.

1:Using 'Create Writer Endpoint' function when used  outside the While loop or inside the For loop allows me to log the data points , but the FPGGA to RT FIFO fills up quickly causing a Timeout on the FPGA to RT FIFO.

2:Using 'Create Writer Endpoint' function inside the While loop but outside the For loop does not cause the Time Out issue, but I am unable to log any data points on the PC.

Analysing this I feel that since I am logging very few data points (i.e. 32 Sample values and 32 Timestamp values) into the Network Stream at a time . Hence, writting very few sample values at a time could cause the FPGA to RT FIFO to fill up quickly. I need to write the entire 2D array of 96,000 elements at a time onto the Network Streams so that may be the FPGA to RT FIFO does not fill up. I do not understand how to implement this  in the current scenario and does Network Streams involve such an overhead for processing.

I have attached the snapshot of the RT VI.

Could you please suggest the right approach for such scenario?

Thanks .

Thanks.

[crossrulz]

You should have the Create Writer Endpoint OUTSIDE of the loop.  Also make sure your Network Stream is being created before you wait for the IRQ from the FPGA.  Assuming your FPGA is waiting for the acknowledge before spitting out data, this will prevent your buffer from filling up before the RT even starts the loop.

[Harss]

Hi,

Thanks a lot for the reply , now I get that the Create Writer Endpoint should be placed outside the While loop. However, I did not quite get the last point which you made that the 'Network Stream should be created before you wait for the IRQ on the FPGA'. How do I implement this on the RT , could you please elaborate on this.

Thanks once again.

[crossrulz]

Use data flow to enforce order.  In this case, use the error wire to make sure the Create Writer Endpoint executes before the checking for the IRQ.