cRIO FPGA input data delay with shared timebase

[charlie87]

Hi,

I am working with cRIO 9082 with modules NI 9229, NI 9230, NI 9234. I read the inputs in the FPGA code. In the setting of the module NI 9229 I checked 'Export the Onborad Clock'  and I set the exported clock as the 'Master Timebase Source' in the setting of the other modules. The sampling frequency is 12500 Hz. I am not sure about the delay of the read data I can expect.

In the datasheets is written

NI 9229:

NI 9230:

NI 9234:

When I compared the equation of the delay for NI 9234 and NI 9229 I was surprised that the equations are pretty same except the operator behind the 1st number 40 (add/multiply).

For the module NI9230 I am not sure what decimation should be used. Can anyone explain to me, how the data should be delayd in the samples to make the data synchronous ???

[l.hovs]

Hi charlie87, 

I found an articlewhere you can understand how to synchronize NI9230. 

The NI-9230 includes an internal master timebase with a frequency of 13.1072 MHz. When using the internal master timebase, the result is data rates of 12.8 kS/s, 11.38 kS/s, 10.24 kS/s, 9.31 kS/s, and so on down to 0.98 kS/s, depending on the decimation rate and the value of the clock divider. However, the data rate must remain within the appropriate data rate range.

The following equation provides the available data rates of the NI-9230:

For more information follow this link. 

Regards)