clear target-scoped FIFO in fpga during run-time

[AndyKr]

Hi,

I am using a target-scoped FIFO in my FPGA to continuously calculate the derivative of a measurement value (dB/dt). Thus the FIFO stores all values during the time dt. This means dt determines the number of elements in the FIFO and dB is determined by the actual value minus the oldest value in the FIFO. It works well when I initialize it with the code in the figure InitFIFO.

But clearing the FIFO is not possible (see figure clearFIFO). In the while loop if "reset dB" is false, the new B value is written to the FIFO and then the oldest value is read from it, so the number of elements in the FIFO stay constant. To change dt during run-time, I need to clear the FIFO and initialize it with a new length (number of elements). I tried the following loop, but this is not working. The FIFO does not get initilized with the elements. The length stays zero and the counter of the for-loop (#deltaB Length2) is 0.

What am I doing wrong? Is there a better way to clear a FIFO during run-time in the FPGA? I am stucked now for 2 days with this problem and looking forward to any idea/suggestion.

Thanks a lot. Best regards

Andy

[taper]

If #deltab Length 2 is 0, then DeltaB FIFO Length must be 0 or 1.  If it's 0 then the For Loop is not executed, DeltaB write node is not run, and default data pushed into #deltab Length 2.  Does your DeltaB have no elements after running this?

[AndyKr · Accepted solution]

Hej,

thank you for your answer. You were correct, DeltaB FIFO Length was 0 because the defalt value was zero. The problem is that in my host vi on the RT system I set DeltaB FIFO Length in a high priority loop and as you can see when I restart the FPGA, DeltaB FIFO Length has a valid value (the code in figure 1 works fine with a local variable of DeltaB FIFO Length in the FPGA). But the variable for setting the "reset dB" variable is controlled from the low priority loop of the host vi. And there I had an unwired DeltaB FIFO Length input. 

So I learned that an unwired read/write FPGA control sends an "0" or resets the variable to its default value in the FPGA. I assumed nothing is transfered and the last variable is kept if you leave a read/write control unwired. Now I learned from this stupid mistake!

Thanks a lot again!

Andy