compilation error

[SaraBaber]

Hello when I try to compile my code it gives me the compilation error!

I have already seen this page

http://digital.ni.com/public.nsf/allkb/311C18E2D635FA338625714700664816

and tried alot to fit in my code! reduced the LUTs usage from 107 to 101%, but it is actually using spline interpolation 4 times seperatly for moving 4 motors! that has got VIs within Vis,

I am also attaching my code!

please have a look into fpga4 reduced and rt4reduced! nad give me suggestions how can i reduce the space and if this compilation error is actually bcz of space! thats the maximum  can reduce the code!! all the motors have to move simaltaneously so I cannot think of using a single spline function moving one and then other motor!

Please find the code and report in the attachmenet1

sara

[DanHarryman]

Hello Sara

I've had a quick look over your FPGA VI, I think one way to reduce the load on the FPGA would be to eliminate the coercion dots. It might also be good to try and use something else apart from local variables from getting one bit of data from one loop to another. This can cause issues as they run at different rates. 

For your RT VI I believe you open a reference to the same FPGA VI more than once this is unnecessary as you can wire the same reference into each part. 

I hope some of this information helps let me know if you have any other questions.

Many thanks

Dan.H

[SaraBaber]

Hello

The coercion dots apperas in first two loops of fpga vi! and for sending data that is compulsory to change the data type I cannot use U represntation as I am moving motors in both CW as well as ACW, so signs are imp for me!

Other than that what should I usr if not local variables for passing data?? basically the main space is not consumed by local varuiables it is consumed by the sub Vi7 and I cannot avoid using it 4 times! if i cahnge the execution properties of this VI it doesnot work fine because actually I think only one value will be working at at time, correct me please if I am wrong!

and reffering to RT vi, does it really matters if I chnage anything in that?? i dont think so because only fpga occupies space on hardware not RT one!

SO how can I reduce it??

[SaraBaber]

IF the local variables are used within SCTL they donot use any memory

ftp://ftp.ni.com/pub/devzone/tut/crio-9074_fpgavi_usage.pdf

so it would be useless to change local variables that are only used in SCTL

[IanS]

Hi Sara,

I had a quick look at your vi's. 

As you say, the RT vi won't affect the FPGA resources, but general good practice is as Dan says, to try and just have 1 reference to the FPGA. You can split this wire and use it in multiple parts, and then just close it once everything is finished, like below:

Looking at the FPGA resources, eliminating coercion dots where you can will save some resources, as the FPGA has to buffer twice.

Try and use fixed point where you can too. Particularly I noticed in the top loop you take an I64 from the FIFO, then split it into 4, which leave 16 bits for each part, but then you convert to a I64 for each one, which is unnecessary, then use the local variable (which is ok to do) to pass the value into a function which requires a fixed point input. Always try and use the smallest data type, as it reduces the number of LUTs for each calculation. I think this will enable you to get the current code onto the FPGA.

I think the SCTL is probably not taking too much resource. I expect most of the resources may be used in the spliner loop, but you can try taking loops out and seeing where the majority of resources are being used, and then focus on reducing those parts.

See how it goes.

[SaraBaber]

Hello

Thanks alot for the detailed reply!

You are right the main resources are used by spline interpolation! when I take that out it works! but I cannot take that out because I have to operate all the four motors! and I cannot use one of them as all have to move at different angles!

I will surely change the data types but that will not help reducing the resources much beacuse its almost 3000-4000 LUTs that are exceeding!

And for reducing these much I am not finding a way out! I havent used any arrays! and all other things take up little resource except this spline interpolation that I think I cannot avoid!

Is there any other way around?

Thanks

Sara

[DanHarryman]

Hi Sara 

I changed the coercion dots on the program and re-compiled the code. This now manages to compile with only using 93.6 of the Slice LUTs. This was done by changing the Math to fixed point. I did leave one coercion dot on the feedback node in the top loop of the program. I'm unsure what this feedback node is doing as It's output only loops back around so I left this. Please look through the VI I have attached and see the screen shot of the successful compilation log. 

Many thanks 

Dan.H

[SaraBaber]

Hello

I have compiled the code given by you although the %utilization has decreased from 107% to 101.7% but still its not fitting in. I have attached the xilion log and error pics!Is this change of space utilization is because I am deploying it on hardware? and only by deploying it actually on harware we will know the LUTs utilization??

What else Can we do for this code to fit in, although its been considerbly reduced now!

Thanks

Sara

[DanHarryman]

Hi Sara

I managed to compile the code by using your project file with a cRIO 9074. So long as you compile code for a specific piece of hardware the compilation won't change if the hardware is not connected. Are you definitely using a cRIO 9074? Also you may wish to remove the VIs from the project under the FPGA target that are not being used. This may reduce the amount used if you compile by deploying the entire project. I don't believe you are doing this but it's still good practice. You can also try to optimize the area the compile worker uses by following the steps on this KB. 

http://digital.ni.com/public.nsf/allkb/EE940C191DDCE9CE86256E5500783A4D

This will make your compilation time increase. 

Many thanks

Dan.H

[SaraBaber]

Hello

I have attached the new project in which I have removed everything else that not required!

My cRio is 9074 and I am even connected with my harware but the results are same!

I am using Labview 2012 and my fpga famliy is Spartan-3,and for area optimizations I cannot find vhdl_area.opt file in Spartan-3, however its avaliable in vertex-5 and that too when i try to change manually it says access denied!

however I If you will see under build specification I have created a compilation file with the method described for former versions of labview!

But still the problem is same 101.5% of LUTs !

Sara