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exponentially weighted moving average on FPGA

Hey,

 

I've tested it and I sometimes get a "jitter" behaviour with the pipelinde version. Therefor I think I will stick to the non pipelined version, as it saves resources.

But I will think about doing the handshaking on my own to ensure right results from the beginning.

 

The multipass is a feature. If you take 2 as a multipass value, the input is running through the filter and the result is running through the filter again. It is like cascading the filter without the need of more ressources. I think there is also no delay, as the new arriving data takes more time then multiple passes of the current input. But this I will have to check. The discrete delay in the case loop is there to follow the transfer function.

 

Thanks a lot for your detailed help 🙂

 

kind regards

 

Slev1n

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