fifo communication problem shifted data

[mathieu35]

Hello,

Currently, there is a communication between a laptop, equiped with a NI cardbus 8310, and a FPGA module controlling an industrial device.
However, we have to transfer this program to a more efficient computer.
The data transfered to the FPGA is sent thanks to a FIFO protocol.
Unfortunately, we met several communication problems while using the main program and the FPGA program :

- We have several error messages such as :

1. -52007 (The most recurrent) : "Called another software component" which happens when we would like to run the FPGA program and when we stop the main program.
2. 61046 : a clock error which occurs at close FPGA VI reference.

- We tried to solve these problems by creating a small program (without the FIFO protocol) aiming to test the communication between the powerfull computer and the FPGA. It worked.

- Then, we created a program (on the computer) including the FIFO communication to test with the FPGA program. It roughly worked but the data were shifted. (This program runs on the laptop but not on the computer)

- Then, we created a new project just to test the communication. It's a simple program in the FPGA :  when we click on OK button, it increments variables and transmits them to the host. In the host.vi, when we valid a button, we say to the FPGA "OK button = true" thus enabling reading of the data from the FPGA. This program has the same FIFO method as the main program but it doesn't work. Actually, in debug mode, we can see variables incrementation but in real time mode, the program blocks in FIFO reading.

- We would like to mention that we have two versions of Labview : labview v8.6 on the laptop and  labview 2009 on the computer.

Hoping that you will be able to help us,

PS : in all test programs, we used the same way to implement the FIFO such as the first program which works on the laptop with labview v8.6.

[christian_w]

What I suppose:

Error 1 occures normally if you set up your bitfile to start when the devices powers up and you try to override a running FPGA.

The solution is to start the device with no app or recompile the bitfile without the startup option and start the FPGA by the Run method.

To your debug problems:

There's an option to debug the FPGA VI's with simulated data. It's not possible to debug the FPGA code by running the FPGA VI's in realtime because it's hardware.

br Christian

[wdhrhe]

hello,

Thank you for your answer,

I understand your answer but the problem we have refers to the fifo. In fact, the program runs well on a laptop

but when we run it on another computer, the data from fifo are shifted. We don't understand why?

Morevover, we did another program with fifo communication and the program blocked during the fifo reading

and we just stop it with the abort program button. Do you know why?

We tested the FPGA program with the simulation and it worked normally.

Best regrads

Mathieu

[christian_w]

Check your FIFO timeout setting. I suggest not to use the timeout setting -1.

[mathieu35]

We tried to put 0, 5, 10, 50, 100, 1000, 2000 and the error -50400 appears.

It says that the transfer didn't complete within the timedout period or within the specified number of retries.

When we set 10000, the program blocks.

[christian_w]

I think you should not wait longer as the outer loop cycle is defined. A timeout normally means the FIFO is empty.

You could use the TimedOut? output for a valid data decision. As soon as the FIFO gets new data, they will be transfered.

I suppose if you wait at the FIFO-Read longer as the loop cycle time you'll get this clock exception.

The 10000 is nearly -1

Hope it helps

Christian