fixed size arrays in FPGA give compilation error - How to implement a waveform control in an FPGA?

[AndyKr]

Hello,

After being stuck for 2 days, please let me shortly describe my project and problem:

I want to use the cRIO FPGA for an iterative control of waveforms. I want to capture one complete period of the waveform, subtract it from a reference waveform period and apply some control algorithm on it. Afterwards the corrected new period should be sent again to the NI output module. If it is working correctly, the captured waveform will look like the reference one after several iterations.

I was planing to create a fixed size array for the capturing and the reference waveform (each around 2000 elements for one period). So I am using 2 arrays of each 2000 elements. I use the "replace array subset" function to update each captured element in the sampling loop and a feedback node for each arrays to keep them in memory (I tried also shift registers, but then the arrays do not have a fixed size any more and I cannot start the compiling process).

If I try to compile the FPGA vi, I get the following error:

Details:
ERROR:Portability:3 - This Xilinx application has run out of memory or has encountered a memory conflict.  Current memory usage is 4167696 kb.  You can try increasing your system's physical or virtual memory.  If you are using a Win32 system, you can increase your application memory from 2GB to 3GB using the /3G switch in your boot.ini file. For more information on this, please refer to Xilinx Answer Record #14932. For technical support on this issue, you can open a WebCase with this project attached at http://www.xilinx.com/support.
Process "Synthesize - XST" failed

Before I added the arrays to my code I could compile the FPGA without problems. So it seems the arrays are too big for the FPGA. 😞

Therefore, I would like to ask if there is maybe a better method for implementing my problem in LabVIEW FPGA? How could I avoid arrays for saving my waveforms over one period?

Thanks a lot for your help in advance.

Best regards

Andreas

[Akiel]

could you post your code so we can have look and possibly make some suggestions?

[Spectre_Dave]

Acquire the signal in the FPGA and DMA it to the Host (PC)

Do your math in the Host.

DMA the new waveform to the FPGA and output this waveform.

Use two seperate DMA channels   Target to Host and Host to target.

[AndyKr]

Hi,

thank you for your fast reply. Please find attached my code where I marked the array creation with green circles and the control part with a red one. I removed all the other stuff and loops which are not relevant here (heart beat loop, value initialization, DMA fifo, etc). The sampling rate should be up to 50kS/s for capturing signals with a frequency of the range of 10 to 500Hz).

@ Spectre Dave:

I would like to do it in the FPGA because my host part (cRIO PPC) is already overloaded and I had a lot of problems to get it running and save the data to a file with the high sampling rate (50kS/s). I was thinking that simple array functions would be an easy thing for an FPGA. Or am I wrong??

Please let me know if you have any idea or if you need more information.

Thank you very much and best regards

Andreas

[Akiel]

Personally i would go with what spectre dave suggested. Once you have captured your data get it onto the host computer to be processed as there are much few limitations like memory and the command set.

[AndyKr]

Hi Akiel,

thanks for your fast replies (overlapping my edit of my previous post).

Unfortunately I have the problem that my host (cRIO PPC) is already at its limit with some math and saving the data to the cRIO disk. So I think I cannot add more math there. This is why I wanted to do it in the FPGA part. The code is mainly just subtracting two arrays and multiplying everything with a correction gain. And this has to be done iterative as a feedback control loop. My PPC is too slow for this 😞

Is this not possible in the FPGA?

Thanks a lot for your help again!

Andreas

[Akiel]

I would have thought it is possible but would depend on exactly which fpga you are using as too how much space and memory. ALso you may have to get creative with the solution as a number of good solutions on a normal pc eat fpgas resources. for example i got rid of some for loops and got my utilization down (I was at 100% at the time so it had to be done) 

search this site for optimising fpga code. A number of good articles come up hopefully some should be relevant to your problem

[Dragis · Accepted solution]

Unfortunately, the LabVIEW FPGA compiler cannot infer embedded memories from arrays (yet). When you create those two large arrays, you are essentially creating several very, very large registers. Just glancing at your image, I would guess there are at least 4 copies of each of the arrays. 

You will want to use LabVIEW FPGA Memories instead. You can create the memories outside the loops and then read/write them where you are currently referencing the arrays. The only change you really need to make is to break your processing down into scalar operations. I have attached a simpler version of your scheme, I hope it helps. Let us know if you have any more questions.

[AndyKr]

Hi Dragis,

thank you for your suggestion and template. I just implemented your solution and the first compiled VI seems to work.Great, you made my day!

Also a big thank for the help from Akiel and Dave.

Now I can mark my problem as solved! 😄

[Dragis]

I'm glad things are working (or at least you are getting closer). Look for new things to come soon that will make arrays easier to use with LabVIEW FPGA ; )