fpga power on reset

[jyang72211]

I have a PCI-7833R. The FPGA is programmed, so that it would supply two digital high constantly.  We had a power outage, and the FGPA was foced to power down.  When I turn the power back on, the FPGA was no longer supplying the two digital high.  I have the following questions:

- It seems to me that the FPGA VI was not running at all after power down.  Shouldn't the FPGA always run? 

- For example, I have a brand new FPGA, and I run an application with FPGA VI, host VI, and bit file.  After that, I let the FPGA runs headlessly.  I assume that the FPGA took on the personality from the bit file of the application that I ran previously.  If that's the case, at what part of the application does it associate the bit file to the FPGA?  

- If I don't have the FPGA module in my LabVIEW, and I receive a bit file from my co-worker, How do I associate the bit file with my FPGA, and have the FPGA runs headlessly?

- After a FPGA is configured to have the personality of a bit file, What are all the ways to clear that or corrupt that?  

- If I have a FPGA that is running headlessly, and I want to do a reset, so that the FPGA runs from the start again.  Is power cycle an option to do that?  Are there any other options?  Can I reset a FPGA without power cycling it?  

Thanks!

[MarcoMauri]

Hi!

Try giving a look here:

http://digital.ni.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9?OpenDocument

Regards,

Marco

[nathand · Accepted solution]

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@jyang72211 wrote:

- It seems to me that the FPGA VI was not running at all after power down.  Shouldn't the FPGA always run? 

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No.  The FPGA loses its configuration when it loses power, and must be reloaded in order to start again.  In most FPGA systems (not just NI) this is done by keeping a copy of the configuration in an EEPROM or similar and loading it at power-up.  Some NI FPGA cards allow you to download a bitfile to the on-board flash memory so that it will be loaded at startup, see Downloading an FPGA VI to the Flash Memory of an FPGA Target.

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jyang72211 wrote:

- For example, I have a brand new FPGA, and I run an application with FPGA VI, host VI, and bit file.  After that, I let the FPGA runs headlessly.  I assume that the FPGA took on the personality from the bit file of the application that I ran previously.  If that's the case, at what part of the application does it associate the bit file to the FPGA?

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I'm not sure what you're asking here.  Within your LabVIEW program you specifically load a bitfile onto the FPGA and run it.  You can also stop the FPGA and load a new bitfile within the same host application - this is useful when you want to accomplish several non-overlapping tasks on the FPGA and there isn't enough space to fit all of them in the same design.

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@jyang72211 wrote:

- If I don't have the FPGA module in my LabVIEW, and I receive a bit file from my co-worker, How do I associate the bit file with my FPGA, and have the FPGA runs headlessly?

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See "Using LabVIEW FPGA Interface without the FPGA Module."  When you headlessly, do you mean with no LabVIEW application running at the same time, or something else?

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jyang72211 wrote:

- After a FPGA is configured to have the personality of a bit file, What are all the ways to clear that or corrupt that?  

- If I have a FPGA that is running headlessly, and I want to do a reset, so that the FPGA runs from the start again.  Is power cycle an option to do that?  Are there any other options?  Can I reset a FPGA without power cycling it? 

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There are LabVIEW FPGA method nodes to abort and reset the FPGA, so you could write a simple LabVIEW application to do this.  I cannot say that's the only way, but it's the only one I know.  I don't know of any way to clear the FPGA without a power cycle, but the reset method might be close enough.

[jyang72211]

Thank!