fpga sequence structure timing problem

[Jasper_B]

Hi,

I am using a sequence structure in a VI on the FPGA of a cRIO-9073. The time each sequence is active is determined the rpm set by the user. In theory each sequence should take the same amount of time but when i check this with a oscilloscope this isnt the case. The signals produced do not have the same duty cycle. When the number of ticks equals 1 in the VI on the FPGA i get a frequency of about 400Hz for the blockwaves at the outputs. I expected this to be much higher since the FPGA works at a clock rate of 40MHz. Why is the frequency of the signals so low and why isnt the duty cycle the same for all the signals ?

Best regards,

Jasper Beurms

[GregFreeman · Accepted solution]

Some of your timing VIs on the FPGA are set to milliseconds, not ticks; in every case but case #2. I expect that is the problem. Double click the VI and change the setting. In fact, why have a wait timer in every case? Just pull it outside the case structure and have 1 instance of the VI in the while loop. Also, whenever I see files named *_<version> it means you probably aren't using source code control. I'd highly recommend it.