fpga vi fails to run when called from host vi

[graduate student 44]

i tried to run Digital(FPGA).vi in fpga examples. i set the target to pxi-7831r instrument. everything runs fine. then i opened Digital(HOST) and set target back to "labview for windows." Digital(HOST) runs fine and it does spawn Digital(FPGA) supposed to be running on hardware. but somehow on the front panel of Digital(FPGA), those push buttons stop reacting.

i tried some other examples involving calling a reference to a fpga vi on the hardware from a host vi. all seem to have the same problem: the fpga vi's seem to be running but no front panel update.

is there any config or any trick one needs to do before using a host vi to spawn a fpga vi on hardware?

[mrak1]

Hi,

This is the normal behavior of the Host and FPGA VI. When you execute the Host VI, the FPGA VI will be downloaded and executed on the FPGA. However, the front panel of the FPGA VI will not be visibly updated like it was in Interactive or Emulation mode.

The FPGA Interface VIs, which are used in the Host VI, interact with the controls and indicators on the FPGA VI. These controls and indicators are updated with the correct values when accessed through the FPGA Interface VIs. Therefore, even though it doesn't appear to be running, the controls and indicators are updated behind the scenes.

Let me know if you need more clarification,

Mike

[graduate student 44]

thanks a lot!

i have several pxi-4472 cards on the same chasis. the master board routes an "AI Trigger" signal to "RTSI0". on the same chasis, i have another pxi-7831R card. do you have any idea how to let the fpga vi running on this card listen to the "RTSI0" line? i tried to make the fpga vi listen to PXI/TRIG0 for a rising edge, but it doesn't seem to work. i'm attaching the code.

[mrak1]

Hi,

Unfortunately, I am not too familiar with the PXI-4472. Regardless, here is my attempt =>

Are you able to receive any triggers? Your application looks good from a first glance. One thing that I did notice was the digital trigger specification in the user manual for the PXI-4472. It states that the minimum digital trigger time for 4472 is spec'd to be 10ns. If your board was generating a pulse at the minimum duration, the FPGA will miss some of these pulses if your application is compiled at 40MHz ( 25ns = 1 clock cycle).

Mike

[graduate student 44]

hi mrak1, i managed to recompile the fpga vi with >100mhz, still doens't work. i realized on my chasis that i have 11 pxi-4472 cards from slot 2 to 12, and the pxi-7831r card on slot 14, with slot 13 empty. does that have any effect on signal triggering? thanks!