I am using Labview 2015 to build FPGA projects. I notice that I have over one hundred files with names like "NiFpgaAG_00000a5f_CustomNodeIPCore_stub.vi" sitting in the root of my C:\ drive, created over the past three months. Each filename is unique with a different hex number before the CustomNodeIP part. The contents of each file look like the below. I get the feeling there is one new file saved here each time I recompile the FPGA code, but they are never cleaned up. Doesn't seem to me like a good programming practice to do this. If a temporary file is needed, why doesn't it go into the normal working directory, or in "Temp" or at least not the C:\ root ? What is your opinion?
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0,Vivado 2014.4_AR64601_AR63880_AR63479_AR62969_(AR63524_AR64594)" *)
module NiFpgaAG_00000a5f_CustomNodeIPCore(CLK, A, B, CE, P);
input CLK;
input [24:0]A;
input [19:0]B;
input CE;
output [44:0]P;
endmodule
