synchro in FPGA module between several FIFOs

[MiguelIrusta]

Dear all,

I have made a project in which I pass data with DMA FIFOs to the FPGA and then return this values without any processing again to the host. I need to do it sequentially, I mean, when the first FIFO is passing the data to the returning data DMA the others must wait while is being send to the host, then the second...an so on. I have done the way is in the picture, but does not work. With only one FIFO (first step in the project) worked right.
Is that the way to synchronize the FIFOs? Should be in a flat sequence all the loops instead of being in separated Flat sequences and without ocurrences?

Thanks in advance.

Kind regards,
Miguel. 

[crossrulz · Accepted solution]

You are actually creating a data dependency with the occurances.  One sequence structure must complete before the next can even start to run.

If you want all of the FIFOs to iterate together, why don't you just put them all inside of the same loop?  Then they will all be read at the same time.

And what hardware are you using?  Many of the hardware only have 3 DMA FIFOs.  Many of the newere ones have 16 (which is what you are using).  Just worried about compilation issues here.

[MiguelIrusta]

Hello,

Firstly thank you for your quick response.

I am working with a FlexRio, PXI 7966R, and as I ahve seen I have 16 DMA, I have used 8 for each side (host and FPGA).

What I was thinking is in order to be reconstruct in the host, will not be problem in the order of arrival if there is no loops?Do you mean that instead of what is made, introduce all the loops in the same flat sequence? Or even put in the same timed loop all the FIFOs without any flat sequence? With the last option won't be any trouble in reconstructing in the host in terms of order?

Thank you for the help.

Best regards,
Miguel.

[crossrulz]

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MiguelIrusta wrote:  Or even put in the same timed loop all the FIFOs without any flat sequence? With the last option won't be any trouble in reconstructing in the host in terms of order?

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That is exactly what I am recommending.  In terms of order on the host, I do not see what that should be an issue.  You are writing to different FIFOs on the FPGA, therefore you are reading different FIFOs on the host.  The data for each FIFO will be in order, so I do not see why you should have an issue on the host with data getting out of order.

[MiguelIrusta]

Dear crossrulz,

Thank you for your advices first of all.

I have done as you told me but I cannot see the results in the host. I don't know if it is due to the timeclock (which is a requierement) or if it is because of other things. Do you think that only linking the tmed out of the last FIFO will result?

Here is a picture of both sides (host and fpga) if you can tell me what is happening and I am not seeing.
Thank you again in advance.

Best regards,

Miguel

[MiguelIrusta]

Changing the time of the timeout works much better. Could be the problem that the writting in the display is much slower than the rest of the processing of the data? If so the plovem will be solved.

Thanks again,

Miguel.

[crossrulz]

Display does tend to be slower than most processing.  But you should know that with a DMA FIFO Read on the host side, it is actually polling for data.  So if you are waiting for data on the DMA FIFO Read, you will be using 100% of your CPU.  But it looks like the processing and returning of the data is fast enough, it should not really matter.