top level clock timing error 0.00 ns

[MWorner]

I am working with Ni 9146 chassis in FPGA.  When the top-level clock was set to default (40 MHz) and the VI was compiled with Xilinx a timing error comes back which states the the time that the code took would be ~0.05 ns, but the expected time was 0.00ns.  Since it was 40 MHz the time required should have been 25ns.  I had the work around that I created a derived clock of 40 MHz, and this makes the compiler think the code needs to run in less than 25ns.  

I do need to know why the default clock does not work though.  

Thank you for your time

Mitchell

[MWorner]

Here are some of the settintgs and error attached

[Wan-L]

Are you using a time loop? If so what are you trying to do in the loop.

[MWorner]

I am using a while loop with a loop timer inside.  This works when the derived clock is used.  There was a few times in which the timing requirment was failed because it ran at ~27 ns, which makes sense that it failed because the requirment is that is runs within 25ns.  The weird part is that when I used the onboard clock asks for a requirment is 0.00 ns.  It does not matter what is within the loop, because no matter what is within the loop it fails the 0.00ns timing restriction.  

Thank you for your time

Mitchell Worner

[VicEngineer]

I have received similar errors in a few of my projects, typically in the past I have simply changed the "Implementation Strategy" from "default" to "reduced compile time". Although I just received the same error 3 times consecutively now and I'm not sure why. I have the exact same VI implemented on another FPGA of the same type which compiles without problem.

I have received two 50pS timing violations and one 980pS timing violation.

Attached are the screen shots of the two most recent errors. Any insight as to the cause?

I just changed the "Implementation Strategy" to "optimize performance" hopefully this rectifies the issue.

[VicEngineer]

So that solution worked, I still don't understand why the device has a timing violation. The VI remained unchanged and I only changed the compilation strategy. Bit of a mystery, any feedback would be helpful