wire from Open FPGA VI Reference Function to CS_cRIO-PB_DP-Master_StartStop.vi is broken

[Steffen01]

Good day,

have some existing Labview 2015 project with FPGA to run a profibus module on a cRIO 9035. Needed to change the PC, re-installed, now the CS_cRIO-PB_DP-MasterExample(Host).vi opens and the wire to the CS_cRIO-PB_DP-Master_StartStop.vi is broken. I tried this

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z0000019LHUSA2&l=en-AU

and configured the Open FPGA reference vi as well, no luck. I get the errors

The type of the source is  (FPGA Interface Dynamic).

The type of the sink is typedef 'CS_cRIO-PB_DP-Master_FPGA-Reference.ctl'

 (FPGA Interface).

or

The type of the source is ( [FPGA Interface]).
The type of the sink is ( [FPGA Interface]).

depending who I configure the open FPGA reference.vi.

Any help would be appreciated.

[LFBaute]

Have you tried creating a control from where you open VI ref...

and replace all controls and indicators all the way through where you use them....

subVIs controls, indicators...etc..

The other thing you can try is casting the FPGA Ref ...using a "Dynamic Interface Cast"

so you would define the FPGA Ref as a typedef.... 

then you would define inside the typedef which bitfile or

VI configure the reference from, that will update all lines.

[Steffen01]

is there a chance, this is related that I had to move to Windows 10? Everything was running fine in Windows 7, just re installed on Windows 10, copied the project across, re-installed everything, re-compiled FPGA for a good measure.

I tried your solutions, It works ok if I don't use dynamic mode. Help says dynamic mode is better if I use the project in multiple places. I don't, its only one place. So worst case I can use not dynamic?

[LFBaute]

So if you recompiled makes me suspect something, even minimum change,

something changed, a control, an indicator, a FIFO or

something defined inside FPGA changed  (vs before recompiling ref)

causing new Bitfile/FPGA VI ref to be different...

and therefore show FPGA ref cable broken...

Using FPGA ref typedef gives you benefit you only update FPGA typedef ref and all FPGA ref changes propagate.

But if its not a matter of propagation

Usually, not always, but most of the time, FPGA ref cable breaks when it doesn't match the definition of what is inside it.

Compare by loading both bitfiles in two separated refs...

and then look at all that is defined inside them

Look at this "Interface" section an compare if something

changed between "before" and after re-compilation bitfiles (or VIs)

This can give you a hint of what is different.

Regarding dynamic mode you can take a look at this post.

"fpga: dynamic mode vs type def for FPGA ref"

[Steffen01]

thats the problem, it was running for 5 years. I never had to touch the FPGA. I  made several changes to the rest of the RT software, always managed to compile and upload to the cRIO. Now the only change is, move the project from Windows 7 to Windows 10. Re-install Labview etc. When I opened it again, the wires broke.

The other possibility is that the profibus start stop vi is from a different library now, and it expects a different input.

If I set to run dynamic mode, the wire breaks