FPGA, Real-Time, DMA FIFO, RIO

[Russ_in_Louisville]

Hi,

I have a hybrid code (which I cannot post here but will use the attached as an example) of a VI on the FPGA target that is just a group of digital inputs. The rest of the code is on the Real-Time target. I understand there needs to be a DMA FIFO to pass information from the FPGA to the Real-Time target so the Real-Time target can share that with the host.

This is a two part question.

1. Why wouldn't the VI that's on the FPGA target be included in the block diagram of the DMA FIFO VI, say in between FPGA Write.vi and FPGA Read.vi, or some other place in the VI that passes through the digital input readings to the RT Target & Host?

2. Also, the RT-Target will need to collect the readings from the VI on the FPGA. Will I just drag in the VI that's on the FPGA into the VI on the RT-Target that's performing the control in my control system, say in a while or time loop and does the VI from the FPGA target need some conditioning in the RT system control VI?

See the note in RT Main.vi --> Timed Loop "I/O Engine"

[trouinky]

You only need a FIFO if you need to stream data without missing a single data point (since typically the FPGA loops will run much faster than the RT loops).

The write/read step on the RT side directly updates the controls and reads from the indicators when the RT loop turn (hence the Reference to the FPGA VI loaded in RT Main). This will happen at whatever rate the RT loop is turning. If you need this to happen faster than the RT loop can turn, then you need a FIFO.

[trouinky]

Another note, when speed is not an issue (measuring temperature for instance), I often bypass the RT controller completely and have the host PC VI read and write to the FPGA directly...

[Russ_in_Louisville]

Tommy,

I understand the example that was uploaded may not represent what is being asked and may confuse matters more than doing good.

1. In my code, the RT Target needs to process data read by the inputs on the FPGA target for the control system to work. The main reason for using the FPGA is because of the high frequency of the input device.

2. There's complex code in my "FPGA Main.vi" to allow for the RIO to read from the input device. So it's not as straight forward as dragging and dropping the I/O on the FPGA target into the FPGA Read.vi and FPGA Write.vi block diagrams, at least I don't think so. I might be wrong.

3. I am assuming the RT Target will be the host so it will have the ability to run headless and the HMI will be only for monitoring and adjusting settings as required. However, I am fairly confident there needs to be a "pass-through" for the HMI to show performance.

So with that said, would I drop my "FPGA Main.vi" into FPGA Read.vi and FPGA Write.vi block diagrams? My "FPGA Main.vi" would have terminals assigned to it and dropped in, in lieu of I/O.

With this goal in mind, is my program a candidate for DMA FIFO?

I was under the impression from the FPGA class that DMA FIFO needs to be included in most FPGA programming with RIO devices and communication with HMIs.

[trouinky]

The zip attached contains a simple project that reads from five digital pins and writes this to a FIFO (the boolean array morphed to an integer).

Sample VI's for reading the FIFO is included with RT and PC-based code, just to show you that you can actually stream FIFO data to either the RT or PC host.... No complaints on the code, I just threw this together as an example to show you where the FIFO write (FPGA) and read (RT/PC) is placed.

You have to balance the RT/PC read speed against the FPGA speed so you don't lose data.  In the past, I've used several methods to grab data out of the FIFO making sure the RT/PC code speed doesn't make me miss any data (the one I included where the remaining amount of data is fed into a shift register is what I use most often). Play with the speed of the FPGA loop in the RT/PC code to see the effects of when the FIFO data get sent in faster and faster for a fixed host loop rate.

You can process data on the FPGA prior to sending to FIFO, and of course you can do this on the RT/PC as well, which I think is preferred, since you can just queue the data as it's pulled out of the FIFO and send it to another loop.

Let me know if this helps. I'm helping out with one project where they are streaming FIFO data to the FPGA for writing at about 100kHz and simultaneously streaming FIFO back out of the FPGA for processing at 4x that rate. The only real issue with speed is splitting the FIFO data correctly, since the data is interleaved from several analog input pins (8)... Good stuff.

TR