CVS 1458RT with 9144 ethercat chassis

[paubine]

Hi,

I want to use an EtherCAT Chassis with a CVS 1458RT. Will I have to dedicated one of the three (1/3) gige port to communicate with the 9144 chassis? So 1 for my gigE Camera, 1 for plant LAN and 1 for EtherCAT chassis?

I know there are EtherCAT drive but I'm working with Allen Bradley, so I think to use a 9263 and a 9411 for analog drive. Could you confirm I will be able to control the analog ouput from the CVS to the EtherCAT chassis at 4ms ?

Thank you

Patrick

[Miro_T]

Your biggest bottle neck will be the scan engine and your code architecture. Check out this white paper to learn more how EtherCAT chassis/modules interacts with a master.

I think 4ms is not bad and it should be doable but you also have to pay attention to your modules. After you finish reading that white paper you will notice that the "maximum rate of your system is always dictated by your slowest component" . In your case you should be good with both 9263 and 9411. It looks like 9263 will be your slowest module but still well within your 4ms requirement. 

t. 

[paubine]

It shoud be fast enough as the CVS 1458RT is a quad-core processor and 9263 and 9411 are really fast too.

The realtime motion timed loop will reside on the CVS and I will use the 9263, 9411 on the 9144 ethercat chassis, samething or similar has if it were on a cRIO?

If I understood, i will have to dedicated use 1 camera gigE port for EtherCAT.

[Rscd27 · Accepted solution]

As T mentioned you should be able to be within the 4 ms you require. I will recommend you not to lower the scan engine from 1 ms.. Also you should be able to control the etherCAT expansion chassis without any troubles. However you must be aware of the limitations of the EtherCAT chassis.

This document is very useful:

https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000YHbbCAG&l=en-US

Also you must be aware that this chassis does not support interactive execution and only allows the use of network variables. Also be aware that you must build the FPGA bit file and deployed from the LabVIEW project.