How to Duplicate IMAQ FPGA Pixel Bus

[jiangliang]

Hello:

I'm new to FPGA Vision, I was trying to compute IMAQ FPGA Centroid, at the same time I want to stream the data to DRAM, also, I want update host image at a lower rate.

I learned the process need to use 4 wire, and seems 4 wire will lock the whole speed of a data stream, I think I need to copy raw Pixel Bus to 2 or even 3 stream, but i didn't found out how to do it, can anyone give me a hint? Thanks a lot!

[jiangliang]

It seems like I will only be able to make one node to use 4 wire handshake, and I will have to handle some of the timing myself, only  make sure the Pixel Bus is feeding the slowest function at the right timing?

But I still not get the point, usually when we using 4 wire handshake function, the later function should be able to cascades additional functions, but many function in Vision FPGA is not like that, they seem like end of a 4-wire handshake function. Which makes it unreasonble when we still need to use the Pixel Bus Data.

For example this function using 4 wire because there are up and down stream terminal, so down stream function knows when upper function is outputting valid data, and down stream function also can notify upper stream function when down stream function is ready.

So we can do this:

but in VISION FPGA function, such as centriod:

 There are only a Pixel Bus In, and there are not Pixel Bus out, how can we using the centroid function do the math and also make this Pixel Bus data reachable for later process?

If I simply  wire the Pixel Bus In to another function, which "ready for input" should I wire to upper stream function?

Thanks!

[AmitShachaf]

If you right click the FIFO element and select Interface --> Handshaking then the FIFO element will expose for you the handshaking signals.

Then you can connect to the centroied function the handshaking signals.

If you want to branch out and connect the a second FIFO to send  the image to the PC in the same time you need to connect the handshaking signals like the second diagram 

[jiangliang]

Thank you, AmitShachaf!

So there still leaves one problem: If the upper stream is coming at a constant rate, and I need to process coming image data using two or three function using down stream function.

For example, using the diagram you provided, if the host is not reading the FIFO fast enough, the centroid function will stops functioning, is that right?

And that not what's I expected, I was hoping I can make sure no upper stream data is lost during the process.

And that only two function we are talking, if I need to stream to DRAM, calc Histgram, Centroied, and DMA to host at the same time, I assume I'll missing some frame from the camera.