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Generate 8 train of pulses with different phase shift from 400Hz input reference using PXI-6251.

Hi All,

 

I want to generate the eight different 5V pulses with 95% duty cycle & each having different phase shift with respect to my input reference using PXI-6251.

 

The input is 400Hz (+/-2Hz tolerance) square wave whose rising edge is my reference for generating the output "train of pulses".

Each output should have seperate phase shift control.

 

As 6251 has only 2 counters & hance I require your help on the same.I also have one PXI-6509 DIO card, but will it be of any help??

 

Thaks in advance.

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Message 1 of 14
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Hi kekin,

 

This example looks like a good starting point: NI-DAQmx: M Series Pulse Width Modulation (PWM)

 

It uses correlated digital output to generate pulses with different duty cycles on four lines simultaneously. Physically connect your 400 Hz clock to PFI0 (or another PFI line), remove the counter/timer code, change the DO sample clock source to "PFI0" (or another PFI line), and modify the DO waveform generation code to adjust the phase instead of the duty cycle.

 

Brad

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Brad Keryan
NI R&D
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Message 2 of 14
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THANKS FOR REPLAY, writing code for phase change is OK since I know that 360 degree corresponds to 1000 points here.

 

But if my PFI0 input is not at 400Hz but if say it varies & changes to 398Hz, the pulse generated at 90 degree phase shift will be at (90*(400/398)) degree.

 

I also want corrections in the pulses as well when frequency changes.Hence I was referring to counter to be used because counter will get reset on the rising edge of input & can also measure the exact frequency & hence I can correct for the frequency tolerance.

 

You said that I should remove the counter/timer part & directly clock from PFI0; but if I clock from PFI0 400Hz signal, then how the count of 1000 samples will arrive without counter?Also the output frequency of pulses is the frequency of input reference i.e.PFI0.

 

Do u have any suggestions?

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Message 3 of 14
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Hi kekin,

 

I misunderstood the purpose of the 400 Hz signal. Does configuring the counter task as finite with a retriggerable digital rising start trigger on PFI0 (but leaving the DO task as continuous) sound closer to what you are talking about? This would have the counter generate (for example) 100 pulses at 40000 Hz every time it sees a rising edge on PFI0. Then the digital output task could output a 100 sample buffer (containing the 8 pulse trains) using the counter output as a clock.

 

How do you expect the system to behave when the 400 Hz signal is running fast? You said you can measure the exact frequency. How soon are you expecting to be able to correct for the frequency tolerance? You can't predict when the next 400 Hz rising edge will occur, so I think it has to be sometime after that.

 

Will some of the pulses you're generating overlap with the next rising edge of the 400 Hz signal?

 

How often are you planning to change the phase shift? (Roughly 400 times a second?) Are the phase shift changes planned out in advance, or are they based on an input signal?

 

Brad

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Brad Keryan
NI R&D
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Message 4 of 14
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Two more ideas:

 

Are you expecting phase-locked loop behavior? The 6251 has a PLL but it cannot synchronize to a reference clock as slow as 400 Hz. Perhaps you could connect an external PLL's output to PFI1, if you could find a suitable one.

 

Also, it would help communicate your requirements if you draw the eight signals you are trying to generate, and how they line up to the 400 Hz reference signal. This could include three periods of the signals, showing the behavior differences: a 400 Hz period, a 398 Hz period, and a 402 Hz period.

 

Brad

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Brad Keryan
NI R&D
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Message 5 of 14
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Question:

How do you expect the system to behave when the 400 Hz signal is running fast? You said you can measure the exact frequency. How soon are you expecting to be able to correct for the frequency tolerance? You can't predict when the next 400 Hz rising edge will occur, so I think it has to be sometime after that.

 

Ans:

When 400Hz signal is running fast say at 402Hz then the pulse which was supposed to be generated at 90 degree of 400Hz signal should be now generated at 90 degree of 402Hz in the next cycle,since my Counter-1 will give me the frequency of previous cycles. COUNTER-0 will be then used to run at (input freq * 100)Hz.

Basically even its like continuous frequency correction that will be applied to fixed phased 8 pulses.


Question:

Will some of the pulses you're generating overlap with the next rising edge of the 400 Hz signal?

 

Ans:

NO they will not overlap. I have taken precautions that if the pulse is to be generated at 0 degree then either it will be generated at 355 degree or at 5 degree.Basically all these pulses will act as trigger for my sample & hold circuits where I am sampling at the peak(one pulse for +ve peak & one for -ve peak) of input Sine waves.

 

 

Question:

How often are you planning to change the phase shift? (Roughly 400 times a second?) Are the phase shift changes planned out in advance, or are they based on an input signal?

 

Ans:

My phase shift for all the 8 pulses are fixed for 400Hz reference signal. Only thing I want is to adapt the phase shift for frequency tolerance.

At least first help me out to generate the 8 pulses for fixed 400Hz frequency. Then we will focus on adaptability part.

 

Question:

Does configuring the counter task as finite with a retriggerable digital rising start trigger on PFI0 (but leaving the DO task as continuous) sound closer to what you are talking about? This would have the counter generate (for example) 100 pulses at 40000 Hz every time it sees a rising edge on PFI0. Then the digital output task could output a 100 sample buffer (containing the 8 pulse trains) using the counter output as a clock.

 

Ans:

I did configured the counter task as finite with retriggerable digital rising edge on PFI0 & DO task as continuous.I used initial delay to generate the phase shift but it didnt work except for first cycle.

 

If I make the array of 100samples for each pulses then I might be able to generate it. But 100 samples will not give me enogh resolution for 360degree. I want atleast 360 samples for 1degree resolution.

 

Can I use SQUARE WAVEFOR.VI to generate reliable phase shifts?

 

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Message 6 of 14
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Hi Kekin,

 

My phase shift for all the 8 pulses are fixed for 400Hz reference signal. Only thing I want is to adapt the phase shift for frequency tolerance.

At least first help me out to generate the 8 pulses for fixed 400Hz frequency. Then we will focus on adaptability part.

 

You can control the phase shift by changing the digital output waveform. Here's an example of what it would look like to generate 4 phase-shifted 50% duty cycle pulses on 4 digital output channels, over the course of 10 samples:

 

 Sample # | P0.0 | P0.1 | P0.2 | P0.3

----------+------+------+------+------

        0 |    1 |    0 |    0 |    0

        1 |    1 |    1 |    0 |    0

        2 |    1 |    1 |    1 |    0

        3 |    1 |    1 |    1 |    1

        4 |    1 |    1 |    1 |    1

        5 |    0 |    1 |    1 |    1

        6 |    0 |    0 |    1 |    1

        7 |    0 |    0 |    0 |    1

        8 |    0 |    0 |    0 |    0

        9 |    0 |    0 |    0 |    0

 

P0.0 has a phase shift of 0 samples, P0.1 has a phase shift of 1 sample, etc. Is this what you're trying to do?

 

I did configured the counter task as finite with retriggerable digital rising edge on PFI0 & DO task as continuous. I used initial delay to generate the phase shift but it didnt work except for first cycle.

 

That is an unfortunate quirk of the counters used on many National Instruments DAQ devices: the initial delay is only used for the first trigger in a retriggerable pulse train generation. This KB has more information: Different Counter Retrigger and Initial Delay Behavior in Traditional (Legacy) NI-DAQ and NI-DAQmx

 

Anyway, setting the initial delay of the counter task only lets you choose one initial delay for all 8 lines. You need to change the waveforms themselves to have per-line control over the delay.

 

If I make the array of 100samples for each pulses then I might be able to generate it. But 100 samples will not give me enogh resolution for 360degree. I want atleast 360 samples for 1degree resolution.

 

If you need more resolution, then use more samples. You could use exactly 360 samples, which would require running the DO sample clock at 144000 S/s. However, 80 MHz / 144 kHz is not an integer, so the counter/timers on M Series cannot generate this frequency without rounding. It will be a compromise.

 

Can I use SQUARE WAVEFOR.VI to generate reliable phase shifts?

 

This VI generates an analog waveform, so it would work for analog output but not digital output.

 

It shouldn't be very difficult to write a VI to generate a waveform like the one I posted in my ASCII art table above.

 

Brad

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Brad Keryan
NI R&D
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Message 7 of 14
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Ques:

You can control the phase shift by changing the digital output waveform. Here's an example of what it would look like to generate 4 phase-shifted 50% duty cycle pulses on 4 digital output channels, over the course of 10 samples:

 

 Sample # | P0.0 | P0.1 | P0.2 | P0.3

----------+------+------+------+------

        0 |    1 |    0 |    0 |    0

        1 |    1 |    1 |    0 |    0

        2 |    1 |    1 |    1 |    0

        3 |    1 |    1 |    1 |    1

        4 |    1 |    1 |    1 |    1

        5 |    0 |    1 |    1 |    1

        6 |    0 |    0 |    1 |    1

        7 |    0 |    0 |    0 |    1

        8 |    0 |    0 |    0 |    0

        9 |    0 |    0 |    0 |    0

 

P0.0 has a phase shift of 0 samples, P0.1 has a phase shift of 1 sample, etc. Is this what you're trying to do?

 

Ans:

I exactly did that yesterday to generate the phase shift by taking 100 points for 360 degree.

 

Ques:

f you need more resolution, then use more samples. You could use exactly 360 samples, which would require running the DO sample clock at 144000 S/s. However, 80 MHz / 144 kHz is not an integer, so the counter/timers on M Series cannot generate this frequency without rounding. It will be a compromise.

 

Ans:

No problem. I can compromise on +/-0.5 degree.Since i am going for 1000 samples for all channels.

 

Ques:

Can I use SQUARE WAVEFORM.VI to generate reliable phase shifts?

 

This VI generates an analog waveform, so it would work for analog output but not digital output.

 

It shouldn't be very difficult to write a VI to generate a waveform like the one I posted in my ASCII art table above.

 

Ans:

I build the waveform exactly as what u mentioned.

I generated the analog waveform from SQUARE WAVEFORM.Vi & then used A to D conversion.VI (with 1 bit resolution & peak to peak 5V) to generate the 1D waveform per channel with different phase shifts.

 Now with this concept how can I use counter1 to measure the previous cycle frequency & apply the same to waveform generator & generate frequency correction & use counter0 to apply reset on every rising edge of input.

 

Also how same frequency correction can be applied if i use the "Build waveform" technique(i.e. one mentioned in ASCII art table)

 

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Message 8 of 14
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Advance apologies for things I may have missed while skimming quickly through the thread.  I want to take a few steps back because if I understand your app's needs, this is going to be considerably harder than you may think.

 

My assumptions:

1. You are measuring the freq of an incoming ~400 Hz signal.

2. In response to the actual measured freq, you want to adjust the phase shift of 8 pulse trains, and you want to put that new shift into effect ASAP (within a cycle or two of the 400 Hz signal?).

3. You want to do this using DIO on the 6251.

4.  All 8 of your output pulse trains should have a freq of ~400 Hz, a 95% duty cycle, and individually adjustable phase shift from the input.

 

Problems:

1.  Timed DIO requires you to fill a buffer of data representing the pulse trains.

2.  Each time you calc a new phase shift that requires a change to the DIO data, you'll need to write new data to the buffer.  HOWEVER, it will not be generated until after all the old data has been generated.

3.  So you're setting up a race where things are at cross purposes.  To minimize delay, you'd like to write only a sample or two at a time into the buffer.  However, that makes you *very* vulnerable to buffer underrun, a DAQmx error that will end your DIO generation task.

4.  And this doesn't even approach the nightmare of trying to make the phase shifts of 8 DIO bits individually adjustable.  There would be a *lot* of bookkeeping to manage to keep track of what the freq was on the last write, how much of each of the 8 pulses' cycles were written on the prev update, how much is left to write to finish their interrupted cycle (which will depend on both the prev and current freq measurements), etc.  Yikes!

 

In short, the 6251 isn't particularly suitable for this job.  I would give *very* serious consideration to a 6602 card with 8 on-board counters.  If you can get one, here's some thoughts on how to proceed:

 

1.  If possible, I'd try to do this by setting up the 8 outputs as retriggerable single pulses.  Also, rather than 95% ON time, I'd make them have 5% ON time with their output polarity inverted.

2. After measuring the input freq (using a counter on the 6251), you can calculate the correct low time and high time for each of your 8 pulse tasks.

3. You'll need to query each task to see if it's ready to accept new pulse specs before trying to write them.  Odds are, you'll find that you can change the pulse specs no more often than once every two cycles.  That's because by the time you measure the freq of cycle N, you are actually already inside cycle N+1 and each pulse task has already been triggered to generate an inverted 5% ON pulse somewhere within cycle N+1.  If you are allowed to write new specs to a given pulse task during cycle N+1, they won't be used until cycle N+2.   When you are in cycle N+2, you'll have just measured the freq of cycle N+1.  However, you won't be even be allowed to write new pulse specs until after the cycle N+2 pulse is generated.  So you won't be allowed to write the new specs until cycle N+3 and they won't be used until cycle N+4.

 

-Kevin P

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Message 9 of 14
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Sorry for so late reply as I was on Outdoor duty.

 

The problem for me now is that I have already used Port 0 of 6251 in my design & now I have to generate these pulses using PFI lines i.e. Port 1 & 2. But these ports do not support BUFFERED operations.

 

Is there any wayout??????????????

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Message 10 of 14
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