Manchester coding/decoding with DAQmx

[Giuvan]

Hi!

I'd like to transmit/receive Manchester coded frames @10Mbps, adapting the VIs explained on http://www.ni.com/example/31126/en/ so that they could process data coming from/to DAQmx. I was thinking of using an M-series DIO PCIe card, which can reach 10Mhz of sample clock frequency: do you think that I can perform such signalling?

[cody_a]

The examples you listed are for one of our FPGA devices, such as an R Series card.  If you purchase a standard DAQ card such as the M-series one you mentioned, the code will not be very helpful (FPGA devices typically use point-by-point algorithms, DAQ devices work on waveforms of data at a time).

That being said, if you're trying to transmit a Manchester coded signal at 10 Mbps, you'll need a DIO clock rate of 20 MHz, right?  Each bit is encoded as a low-to-high transition or high-to-low transition, and therefore each bit actually takes two clock ticks to transmit/receive.

We don't have any multifunction cards with a 20MHz DIO clock rate, so you'll need to check out either a FPGA based device like I mentioned above or use a low-cost High-Speed DIO series card like the PCIe-6536B.  If you only need to receive the Manchester signal at 10 Mbps, you could use a counter input task for that, but it wouldn't be as straightforward as using the DIO lines, and generation of the signal would not be possible.

[Giuvan]

Hi Cody, thank you for answering!

I'm aware of the lower level programming involved in FPGA compared the the one I'm gonna use, I was just taking those VIs as a starting point to be adapted to my case.

As for the bitrate, I meant that 10Mbps is the rate at which the already manchester coded frame has to be sent.

For instance, if a message 1111 has to be sent, its Manchester coded frame becomes 10101010 and this one is transmitted at 10Mbps over a channel, hence I think that an M-series board would be capable of that... Given a fixed transmission time, the manchester coded frame requires twice the bitrate compared to the bare message, but 10Mbps is the figure already doubled up!

My concerns were more about whether DAQmx can handle such rate: even though there's not much this VI has to do, the timing is kinda tight!

[Giuvan]

I'm curious about your advice of using a counter task for receiving a manchester coded frame: could you fill me in?

My concerns about receiving a 10Mbps signalling comes from the fact that M series boards have an hardware FIFO of 2,047 samples: if acquiring @10Mbps, assuming that we want to empty the buffer when it reaches 2,000 samples, we would have to call the DAQmx read.vi block every 200 microseconds. However, wen it gets to creating a producer loop  in order to carry out this acquisition, timing blocks like "wait" or "wait until next multiple" won't allow us to set a loop time below 1ms. So althought the hardware is capable of acquiring at such rate, it seems that there's a software bottle neck: is this just my impression or there's another way to implement this? Thanks again advance to whoever can give me a hand!

[Giuvan]

Ok, I got the board's FIFO buffer mixed with the PC buffer

Considering that a PCI bus allows a rate of 133MB/s I won't have to be concerned about that interface, and given that the PC buffer has plenty of space, I can easily call recursively the read function with a loop time in the ms range!