UB differential pair groups should be able to specify how close to equal length is required.

[dbur]

UB differential pair groups should be able to specify how close to equal length is required.

There is almost always some amount of length matching error.  Not being able to specify allowed error means you will always get a DRC when you have matched length nets.

[ERC-]

Hi,

I have been using Multisim and Ultiboard for long time and I am really expert on it, so I have some suggestions so I will post them one by one.

My first suggestion is:

Ultiboard High Speed routing parameters never meet track length constraints. Most of my designs are high-speed at minimum 4-layers pcbs and I use impedance paramters of ultiboard to match the track lengths. After I setup everything, making the track lengths are almost impossible and DRC warns as not matching the lengths. What I think is, Ultiboard team should add "Serpantine" option to make zig-zag tracks to match the lengths. I do it manually by using graphics->"ARC" shape tracks and this is really annoying, so we should have "serpantine track" option in the menu and showing the length at real-time while we move the serpantine track. This can make the ultiboard state of art tool.