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修改时间 02-28-2019 01:25 AM
我需要在FPGA上实现如图的 FIR加窗滤波器 的控件功能,请问如何使用FPGA模块中的 FIR Compiler 7.2 进行配置。
已解决! 转到解答。
03-01-2019 12:37 AM - 编辑日期 03-01-2019 12:43 AM
您好,
FIR Compiler 7.2 是这一个吗?
https://www.xilinx.com/support/documentation/ip_documentation/fir_compiler/v7_2/pg149-fir-compiler.p...
LabVIEW Communications 也有创建Filter的功能:http://www.ni.com/documentation/en/labview-comms/latest/analysis-node-ref/filter-design-windowed-fir...
修改时间 03-03-2019 07:37 PM
是 FIR Compiler 7.2
修改时间 03-03-2019 07:38 PM
这个手册看上去好复杂。。。。
修改时间 05-21-2019 03:38 AM
我想下问下您实现了么?我也遇到同样的问题。
修改时间 05-21-2019 04:03 AM
给你个网址 http://xilinx.eetrend.com/d6-xilinx/article/2017-07/11743.html
修改时间 08-28-2024 01:31 AM
哥,你这个网址失效了。。我现在也想用labview FPGA去实现一个FIR滤波器
What do you need our team of experts to assist you with?
Thanks!
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