Hi There,
I've inherited some FPGA code that originated from NI that implements an "IIR Cascaded Second-Order Sections Form II Transposed" filter that one of our customers have used for years as an FPGA personality called by Veristand. It is very similar to the IIR_SOS_FPGAVI.vi within the "Cascaded Second-Order Sections IIR.lvproj" example in LabVIEW 2016.
We've had a problem bench, and I've been investigating. I think I have a solution to the problem (waiting for an opportunity to travel to customer site), but since we use this filter a lot, I would like to get this it into a better development environment so that I can tell what is going on with it.
For starters, I would like to run this FPGA code in simulation execution mode. I've attempted to use the Diagram Disable Structure to poke in some simulated inputs and read some outputs from the front panel. At some point I had the simulation working right, but now I've got the input FIFO overflowing. The overflow seems to be related the handshaking in the filter. Fortunately, one difference between my code and the example is that the filter code is exposed instead of being wrapped up in a VI generated by "IP Builder". I guess probably because it is older, maybe 2010 vintage. But unfortunately, the filter is complicated enough that I just can't figure out what it is doing. I would like to resolve the FIFO overflow issue.
I've contacted my sales person, and he said the original person involved with this filter has left the company. However, it doesn't seem to be an isolated piece of code but something that has been reused at NI. The "Cascaded Second-Order Sections IIR.lvproj" example is a case in point. There are also several NI articles about this, such as this article. I am hoping to find somebody that knows something about this filter. Perhaps Lei Song, Staff Engineer, LabVIEW FPGA R&D? Thank you.
