05-08-2013 02:39 PM
06-27-2013 01:50 PM
Hi Stephen
We (I and the customer) are trying to use the PXIe-6674T and PXIe-6672 with Veristand.
We did the steps following the below link
https://decibel.ni.com/content/docs/DOC-29546
But we dont know how we set the parameters to generate a sample clock using the pins PFIx (0 to 5) (6674T), and how we can set to synchronize using 6672.
We were trying to do into LabVIEW and I opened an escalation
NIC SR 2029355
Because of the Reflectve Memory, the customer changed the project to Veristand.
Do you have some Veristand example project to master (generate sample clock with 1MHz) and slave (to synchronize with the master)?
Thank you
06-27-2013 01:59 PM
Hi Anderson_Takemoto,
Could you provide some information about the goals of using these devices? Are you trying to sync two PXIe chassis together for use with NI VeriStand or are you trying to do something else?
This custom device is for synchronizing the PXI and RT clock of a single chassis with a PXI-6682 or between multiple chassis with a PXI-6682 and a PXIe-6674T or PXI-6653.
06-27-2013 02:26 PM
The goals are synchronization of 3 PXI chassis: 1 master and 2 slaves using Veristand. All has Reflective Memory (GE 5565 PIORC).
The master has PXIe-6674T, for now we need 3 output not differential with 1 MHz clock to synchronize the slaves.
Each slave has the PXIe-6672.
We need to synchronize the clock without drift between master and slaves.
Thank you to answer very fast!
06-27-2013 02:29 PM
Thanks for the information
Does each chassis have a controller? What hardware is in each chassis?
06-27-2013 02:38 PM
Master:
Chassis PXIe-1062
Controller: PXIe-8135
Devices: 5565PIORC, PXIe-6674T
Slaves:
Chassis: PXIe-1085
Controller: PXIe-8135
Devices: 5565PIORC, PXIe-6672, PXI-6725, FASTCOM, PXI-8430, PXI-8431, PXI-6341, PXI-6723
The difference between slaves are the number of devices.
06-27-2013 02:43 PM
So the master has no IO cards?
06-27-2013 02:45 PM
06-27-2013 02:46 PM
What is a PXI-6725?
11-04-2013 10:02 AM
From Usman:
Stephen,
I followed the steps listed and tried to deploy but I get an error message saying the VI is not executable. Could you please contact me and I can go over this? As soon as I remove the Chassis TimeSync under timing and Sync, I could deploy the sys def.
Thank you
Usman,
I have some other things to try but those are the beginning.