Engine Simulation Custom Device Feedback

[isabella2]

Stephen,

I tried debugging using the method you suggested. The  VS values are not passed on to LV.

[StephenB]

Few questions:

1. Can you screen shot the front panel of the FPGA VI so I can see the control values?
2. What is the value of the channels under the engine simulation "Stuatus Channels" section? Can you take a screen shot with the channel data viewer tool in the workspace?
3. If you take the example project that comes with the download and compile it for your target, does it work? I'm running it right now and it is working fine.

[isabella2]

Stephen,

I am compiling the example VS/FPGA model. Will update you on my progress

Thanks

[Leo_Lemes]

Hi guys,

I'm having some problems with FPGA compilation. I get the error about the capacity of LUTs available for logic. So I tried change the Xilinx Options as Stephen suggested in one of their posts and didn't work. After, I changed the part of the code (I divided the code in "N Teeth M Missing Generation Loop") and didn't work too.

As last attempt I tried compile the default code (Engine Sim FPGA Example.vi) and I got the same error.

I'm using 7851R, VS 2011, LV 2011 and Engine Custom Device 3.5 version.
I put my project attached.

Tks in advance.

Leonardo Lemes

[StephenB]

Unfortunatley it appears your target isnt big enough. That is the smallest FPGA you can buy.

You can either:

1. get a bigger target
2. try to optimize the code
3. Remove the parts you're not using. For example, the template adds in all of the event information. For your specific application you may only need end angle for IC events

[Leo_Lemes]

Hi Stephen,

First of all, thank you for your help.

And you right! I reduced by half the number of ECU Events in Fuel Injector Loop and Ignition Coil Loop. Thus, the compilation works!

I did the process that you suggest in one of your posts to debug and the system works well! But I had a little problem when I undeployed the system, I got the following error and the VS closed.

Well, I got this error when I was doing another CD and the problem was in RT Engine VI. But in this case I don't believe this could be the problem. Do you have any idea?

[StephenB]

Unfortunatley that is a LabVIEW 2011 SP1 bug. It gets a little better if you install NI VeriStand 2011 SP1

[Leo_Lemes]

Hi Stephen,

I was using LV 2011 and VS 2011. So I did what you suggested, just installed VS 2011 SP1 and works very well without problems!!!!!

One more time, thank you very much for your help!!!

Leonardo Lemes

[Leo_Lemes]

Hi guys,

I would like to know if we can simulate the Vehicle Speed signal. The customer already tried simulate a square wave with a function generator (no NI hardware), but didn't work correctly. The pointer was instable in the cluster.

Someone already do that?

Best regards,

Leonardo Lemes

[ToddK]

Leonardo,

I have a working example of a simulated speed sensor signal using a NI-9474 DIO module and FPGA personality. Used 2 VeriStand channels for shaft RPM and Sensor Wheel Teeth to calculate the square wave pulse generation packets.  The Pulse Generation template is available within the LabVIEW palate under VeriStand FPGA Support/RIO Library/IP Based IO/Pulse Generation.

Todd Kutzner – Digalog Systems Inc.