Error code -61200 when deploying to target?

[cabala]

Does anyone know why this error would be generated when trying to deploy the veristand system definition file to the target? The only information i can find is the list of error codes which just states the same thing as in the log.

I don't see any options when generating the bitfile that would cause this or in the veristand project or in MAX. How do I stop all activity on the FPGA's and what does that even mean?

Details:
Error -61200 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Possible reason(s):

LabVIEW FPGA:  The operation could not be performed because the FPGA is busy operating in FPGA Interface C API mode. Stop all activities on the FPGA before requesting this operation.

[Jiri_K]

This code probably uses following library https://decibel.ni.com/content/docs/DOC-17185.

It happens, that the operation of FPGA is stopped and the reference from this library is not properly closed.

Target reboot helps to release reference. You should check for the reference closing code, to properly handle this part.