Arranging multiple synchronized digitizer and signal generators in PXI system

[gregoryng]

I am trying to extend a synchronized generation/acquisition application to more devices, and wanted to see if there are any performance implications with some of the possible choices.

I have an existing working application that has a synchronized PXI-5422 signal generator in slot 4 and PXIe-5122 digitizer in slot 6 of a PXIe-1075 chassis.  They use NI-TCLK for synchronized generation and acquisition. The 5422 gets a digital edge trigger from another card, and then the 5422 generates a start marker on PXI_Trig5 that the PXIe-5122 uses.

I have also extended this with another PXI-5422 in slot 15 and PXIe-5122 in slot 14, with the same arrangement.  I don't know how the PXI-5422 in slot 15 receives its trigger, but I pass its reference to the NI TCLK routines and I assume that the tclk VI somehow takes care of that for me (perhaps someone could explain?).  PXI-5422 in slot 15 generates a start marker on PXI_Trig5 which the PXIe-5122 in slot 14 uses.

I also tried a version where I remove the PXI-5422 in slot 15 and programatically routing the PXI trigger on PXI_Trig5 (generated by slot 4) across the backplane segments to slot 15.  That seems to work fine.

Are there any data performance or trigger timing implications in how I arrange my cards?  For example if I put two digitizers next to each other, will their relative timing be less jittery than if far apart?  If so, what's the order of magnitude?  

If I put two digitizers next to each other (e.g., slot 6 and slot 7), will that affect the data bandwidth or latency to the CPU?  If so, what what are we talking about? FYI, I'm expecting records about 70us long at 50 MS/s, at a rate of about  6000 records per second, from each digitizer.

It seems like things would all be simpler if I just put all the digitizers together, but I wanted to know if there's a limit to this and how I would know if I'm running up against it.

[TommyDunkz]

Hi gregoryng,

What is the clock source in your existing application? Are you using a timing card to generate a clock signal?

[gregoryng]

Yes, there are two configurations.  Originally I had been using a PXIe-6672 in the timing slot (10), but I've also been testing a configuration where I'm using a PXI-6602 counter output from slot 3 to generate the 6 KHz clock signal.  As far as I'm concerned, they both seem to have similar performance since their underlying clock source is the internal PXI 10 MHz clock.  

[TommyDunkz]

Hi gregoryng,

If you're using the chassis' backplane clock, you won't have to worry about increased jitter in either case. All of the lines on the backplane have the same trace length, so the clock signal should be synchronized to specification at each slot. See the KnowledgeBase to which I have linked below for information on how to calculate the accuracy of the clock signal.

Frequency Error and Frequency Measurement of Generation Accuracy: http://digital.ni.com/public.nsf/allkb/2A0B9D3F365DEDEF86256BDB007354ED