Power Electronics Development Center
Solar PV Power Converter and I-V Characterization Examples
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Aromero2284
Please find attached several solar photovoltaic (PV) power converter and I-V characterization examples.
1. PV Panel Simulation and I-V Chararacterization (PV_Simulation_and_IV_Characterization.vi)
This includes solar cell I-V characterization code, which originated with NREL in their outdoor solar test facility and was edited/updated by NI systems engineers, and a classic PV model equation solved in LabVIEW using the Newton Raphson method. As you mouse over various items on the front panel, educational information is displayed. You can change the series and shunt resistance of the solar cell as well as the illumination level, and observe the effect on the I-V curve and P-V curve for the solar cell.
2. Solar Array I-V Characterization using Resistive Load
In this example, a PV array is modeled in Multisim with the resistance controlled by LabVIEW. The LabVIEW co-simulation application sweeps the panel from short circuit to open circuit conditions while recording an array of voltage and current data. Then the I-V curve data is passed to the solar cell characterization algorithms and the solar array is characterized, including short circuit current, open circuit voltage, fill factor, series and shunt resistance, maximum power, maximum voltage, maximum current and efficiency. The P-V and I-V curves for the solar array are also traced.
The PV array model in this Multisim example is based on J.A. Gow M and C.D. Manning. "Development of a photovoltaic array model for use in power-electronics simulation studies " IEEE Proceedings of Electric Power Applications, Vol. 146, No. 2, March 1999.
Note that a number of alternative solar photovoltaic (PV) models are available for Multisim, as described in this application note:
3. Solar PV Boost Converter with Maximum Power Point Tracking (Solar PV Boost Converter with MPPT.vi)
In this example a solar PV boost converter circuit is modeled in Multisim and the sime "Analog RCC Method" is used for maximum power point tracking. Note that the fixed point version of the algorithm needs work. I'd recommend implementing the FPGA control system using the FPGA Graphical Floating Point Toolkit.
Note: The FPGA code should be simulated using the LabVIEW FPGA Desktop Execution Node.
4. Solar PV Single Phase Grid Tied Inverter Controller
In this example, a solar PV array is connected to a full bridge power converter controlled by LabVIEW FPGA.
Note: The FPGA code should be simulated using the LabVIEW FPGA Desktop Execution Node.
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Content Cleaner
A LabVIEW 2013 version of the solar PV applications is attached.
If you want to upgrade to LabVIEW 2014, there a lot of usability improvements for LabVIEW FPGA co-simulation using the Desktop Execution Node.
Follow this link to web downloaders for the entire toolchain (including the new Multisim 2014): 'What tools do I need to get started developing a power converter product?'
If you are interested in complete power electronics control example code for a PV array with boost converter stage, maximum power point tracking (MPPT) and unity power factor 3-phase inverter interface to the grid, I highly recommend StarSim by ModelingTech. StarSim for Windows is a desktop co-simulation tool for control design and power electronics & power system simulation. StarSim also has a real-time HIL simulation version for validation and verification testing of your control system.
Once you install StarSim for Windows, you'll find the example code here: C:\Program Files (x86)\ModelingTech\StarSim\1.5\Examples\Solar Power
Here is a screenshot of a simulation run with maximum power point tracking enabled. As you can see, the control system is successfully tracking the maximum power point and is providing only active power to the grid (unity power factor).
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Here is the LabVIEW control code, which includes synchronous reference frame (dq axis) 3-phase 2-level inverter control for the grid interface, maximum power point tracking boost converter control, and single-triangle pulse width modulation, and a solar PV array model.
The StarSim circuit model includes the IGBT boost converter, 2-level IGBT 3-phase inverter, line reactor filter, local three phase reactive load, 100 meter 3-phase transmission lines, and 380 Vrms, 50 Hz 3-phase grid.
If you want to convert the control code to an FPGA version that will run on the NI General Purpose Inverter Controller (GPIC) or NI CompactRIO, use the LabVIEW FPGA graphical floating point tool to convert the math operators to single-precision, non-reentrant subVIs. You will first need to unlock the password protected control IP cores by purchasing StarSim for Windows by ModelingTech, then email info@modeling-tech.com with proof of purchase to obtain the password. For more information about StarSim, visit: http://www.modeling-tech.com/English/index.aspx
Here is a screenshot of a 3-phase bidirectional AFE inverter control application running on the GPIC in DC bus voltage regulation mode and reactive power setpoint of 0. This is the actual waveforms from the physical inverter running-- not a simulation. Below is the front panel of the LabVIEW Real-Time application.
There is an energy storage half-bridge buck boost battery storage converter connected to the DC link, so but running the active front end in DC link voltage regulation mode the power is automatically transferred to the grid in the case that we are discharging the battery, and automatically pulled from the grid in the case that we are charging the battery.
Here is the front panel of the FPGA application. All of the control algorithms, sine-triangle PWM and protection logic is running in dedicated FPGA hardware using floating point math functions. The main control loop is running at 33.3 kHz (1200 ticks), and the sine-triangle PWM loop is running at 1.33 MHz (30 ticks).
Here is the block diagram of the LabVIEW FPGA control application. It's wonderful that when you program in floating point, the control code looks like how you would draw it on a chalk board. Yet, it is running in high speed in dedicated FPGA hardware where each loop can execute truly in a hardware parallel way.
Bottom loop (fault handling):
