Configuring the ADC on NI 5752

[Simplicity_Jon]

Hi I am developing a FlexRIO application with a PXIe-7965 and the 5752 Adapter. I Have some questions about the TI AFE5801 ADC. In the datasheet for the ADC it says that you can link two channels together and perform averaging in the ADC chip itself to get better SNR at the expense of channel count. Is this possible with the adapter or is there other electronics inside which would prevent this? Also the NI example shows how to set the digital gain (which are settable per channel) but not the Coarse and fine gain. There seems to be only one set of registers for the coarse and fine gain so I assume it applies to all channels. There is also mention of Time Gain Control (TGC) I am not sure what this actually does but assume you have to set it to Static PGA for it to work as a normal Variable gain amplifier. I am also not sure what the use of the digital gain is as it is performed after the the ADC.

There is not much documentation on the 5752 apart from the ADC datasheet so any info would be helpful.

Jon

[jonlee]

Hi Jon,

I have not tried the averaging to improve SNR, but there shouldn't be anything in the NI 5752 preventing you from doing this.

The TGC allows you to create a profile to adjust the VGA versus time.  This is done by specifying what gain you would like and for how long.  After the duration has elapsed, the gain will be adjusted with the next gain setting you specified along with its duration, and so on.  This allows you to deterministically adjust the gain synchronous to the ADC's samples.  If you would like to set a single gain value you would use the Static PGA setting.

Regards,

Jonathan

[mittu1]

Hello,

Can you help me by suggesting how i can control the gain of afe5801. I dont need variable gain, i need to have maximum gain that afe5801 can provide. How i can program this? I am very new to this.

Thank you,

Mithun

[jonlee]

Hi Mithun,

If you open up Example Finder in LabView and search for 5752 you'll find an example called NI 5752 Configure ADC. This example allows you to change the gain of the ADC. You can take a look at the block diagram and see where the gain is being programmed and relate that back to the AFE5801 datasheet if you would like to see how we came up with those values.

Jonathan

[mittu1]

Hi Jonathan,

Thank you for the response. I already went rhough that example. What exactly digital gain is? There is option to program the gain to 31 db.Isnt it?How to achieve this ?

Thanks,

Mithun

[jonlee]

Hi Mithun,

Digital gain allows you to change the gain of each channel. Here is the description:

DIGITAL_GAIN_ENABLE
Address: 3[12]
Setting this bit to 1 applies to each channel i the corresponding gain given by DIG_GAINi<15:11>. The gain
is given as 0dB + 0.2dB × DIG_GAINi<15:11>. For instance, if DIG_GAIN5<15:11> = 3, channel 5 is
increased by 0.6dB gain. DIG_GAINi<15:11> = 31 produces the same effect as DIG_GAINi<15:11> = 30,
setting the gain of channel i to 6dB.

I think what you are referring to is controllable with the TGC registers. I believe you want to use the static PGA mode along with the coarse and fine gain 

STATIC_PGA
Address 0x99[3]
Setting this bit to 1 disables the TGC engine. COARSE_GAIN and FINE_GAIN control the gain value, which
is independent of time.  

COARSE_GAIN
Address 0x9A[5:0]
This 6 bit register specifies the coarse gain from –5 to 31dB, in 1dB steps. Observe that only values from
0x00 to 0x24, both included, are valid. Setting a value bigger than 0x24 on the COARSE_GAIN register is
the same as setting 0x24. COARSE_GAIN = [–5 + REG_VALUE ] dB
REG_VALUE GAIN
0x0 –5dB
0x1 –4dB
0x24 31dB

FINE_GAIN
Address 0x99[2:0]
This 3 bit register specifies the fine gain in steps of 0.125dB resolution, from 0dB to 0.875dB. FINE_GAIN =
[0.125 × REG_VALUE ] dB
REG_VALUE GAIN
0x0 0dB
0x1 0.125dB
0x7 0.875dB

I don't think it's explicitly described, but I also believe you need to set INTERP_ENABLE = 1.

Jonathan

[mittu1]

Hi Jonathan,

Thats really a nice information.Yes i would like to have STATIC_PGA and i tried everything except INTERP_ENABLE = 1. It is yet to work. Hope it will work once this bit is set. Once again thanks and i will update here once after checking tomorrow....

Thanks,

Mithun

[mittu1]

Dear Jonathan,

INTERP_ENABLE is related to static PGA_SETTING? Why?

Mithun

[Erwin1]

Dear Jonathan,

I tried what you said and it is not working for me. What i am trying to do is adding gain control functionality in the Multi recordtrigger example. Digital gain control i tried and it is working. But static PGA setting is not coming out well.Can you suggest me any idea to move forward.

Thanks,

Mithun

[blum22]

Dear all,

I am a little late on this topic, but it is very relevant to my current application. I am using a 5752 for the acquisition of ultrasonic signals, and I see a frequency-dependant behavior in my 5752 signal compared to visualizing it on an oscilloscope. I have tried to do an AdcRegisterReset on the module before the acquisition, but I still see the same freq behavior. I have look at the AFE5801 doc, it mentions an antialias filter but the cuttoff is higher that my bandwidth on interest.

After looking at the NI 5752 configure ADC example I have a hard time understanding how I can easily set the lowpass cutoff frequency as well as a fixed gain for all channels. Is there another example out there that would show me how to achieve that?

Thanks,

Thomas

PS: I am working on getting the exact frequency response as I write, I will post an update when I have it.