DMA FIFO buffer clearing - Transfer between FPGA target and RT host

[bogdan_ETH]

Hello,

I am experiencing some trouble understanding how DMA FIFOs work. Here are the details of my project:

- Hardware: cRIO 9074 with FPGA

- FPGA project with 2 VIs: one for RT host and one for FPGA target

- I am trying to perform the following: read an analog value (position encoder) on the FPGA at 2kHz and transfer the data to the RT host for saving in a TDMS file. The RT host loop is set to run at 500Hz (0.5kHz), the number of FIFO elements on the RT host side is 10,000 and the one on the FPGA target side is 1023.

- From my understanding and what I have read around the internet, since the FPGA loop is running 4 times faster than the RT loop and the FIFO size is almost 10 times bigger on the RT than the FPGA, there should not be any problems (i.e. the RT “FIFO Read” should be able to keep up with the FPGA “FIFO Write”).

- With my code (attached here) I can only retrieve 10,000 elements, i.e. data for only 5 seconds (FPGA loop running at 2kHz) and then the “Overflow” turns to “TRUE” indicating that the FIFO on the FPGA is full (caused by the fact that the information is not retrieved  anymore on the RT loop) . My question is how can I continuously retrieve information? For example, if I want to read and store data for 30sec continuously at 2kHz (i.e. to record 30 x 2,000 = 60,000 data points)? I assume there should be some way to clear the FIFO buffer after each iteration?!? Any suggestions on where I can find examples with code implemented in this direction?

- On the same topic (FIFOs), but another question: How can I “flush” the old data in the FPGA FIFO? Right now every time I start a new recording it transfers to the RT host FIFO first 1023 elements from the old recording and then the rest of the elements up to 10,000 are filled up with data from the current recording. I tried (as suggested on the forum in other topics) adding “FIFO Stop” and “FPGA Reset” (as you can see on the RT host diagram) but it doesn’t work.

Thank you and best regards,

Bogdan

[RupiDo]

Hi Bogdan,

thanks for your detailled description regarding communication issue between RT host and FPGA target.

1. flush the old data

Basically when  an RT - FPGA application should stop the execution first of all the FPGA loop should stop. Then use in RT Host VI twice the FIFO Read Invoke node. The first only node only retrieves the remaining available elements in the fifo. The next FIFO Read Invoke node read all this elements.

Please be aware, the reset invoke node clears the DMA FIFO. I attached a screenshot about a RT host reference example.

2. FPGA RT communication

Your thoughts about planning the size of the FPGA DMA FIFO and RT DMA FIFO are completely right. The RT FIFO size should be the write rate of FPGA/ read rate of RT host * security factor (1,2).

Please keep in mind between FPGA and RT Host a PCI bus transfers the data. So the bandwith of the bus is 132MB/s. But in your case you never reach this limit. So there shoud be another reason for the timeout behaviour

Please check also this reference example about streaming data

Reference Example for Streaming Data from FPGA to cRIO to Windows

http://www.ni.com/example/30919/en/

Change also the timing, the first sequence frame should include the timing, the 2nd one the programm code. If you don't change the frame order, the first 2 iterations are executing directly and not in a loop rate of 500µs.

Kind regards,

RupiDo