Downloading and running labview bit files to single board rio FPGA

[9845567540]

What is the means of communication between Host computer (Dev PC) and the SB-RIO target?

Does single board RIO devices be controlled from the host, the same way as R-series devices? .

Can we implement a FIFO through the ethernet port to transfer data between the host computer and the Target?

I need a FPGA Digital I/O for my application to communicate with peripherals on an embedded board. I was initially thinking of going with the R-series board, but the cable length is coming in the picture. I have already designed and fabricated the adapter for the board. So the R series board solution will have its own cable (68 pin VHDCl connector to 68-pin D connector) + custom interface (between the previous connector to the connector in the adapter. This will also have level translation from 3.3V to 5V environment) + adapter to target board cable. Since there are too many variables, I am not sure whether the signal integrity will get affected.

The sb rio board provides all the necessary DIOs required + no need of signal conditioning as all the DIOs pass through a

SN74CBTD3384C as per specs. I can now directly connect my target hardware to the Sb rio device by using a daughter board on the RIO card. In this case, I only need a communication interface like ethernet between the Host and the FPGA to implement a mailbox register kind of FIFO.

Please provide some answers to clarify the issues. I am as looking for a detailed manual on how to operate these devices so as to try and see if these single board rio devices fit my requirements.

Looking forward to some help.

Thanks in advance.

Vijay

[Christian_L]

The sbRIO is an enclosure-less version of CompactRIO (cRIO), so in fact the sbRIO target is really two LabVIEW targets in one, a LabVIEW Real-Time target and a LabVIEW FPGA target. So it is a bit different than the R series card which is only a LabVIEW FPGA target.

Normally you program cRIO/sbRIO targets using LabVIEW RT and LabVIEW FPGA.

• In your LV project you create a RT target for the RT controller on the sbRIO.
• Then within the RT target you create the FPGA target.
• You then create VIs to run on the FPGA, you compile and can test them interactively.
• Next you create VIs to run on the RT controller. They can communicate with the VI on the FPGA like you have done in the past with your R series cards. The RT VI s can communicate over Ethernet with your host VI running on Windows using Shared Variables, TCP communication and a variety of other tools.

If you do not need any code to run on the RT target, the NI-RIO driver does allow you to interact directly from your host Windows LabVIEW VI to the FPGA on sbRIO, similar to how you are communicating with the R series target. This is done over Ethernet by using a remote RIO target in NI-RIO. This communication does not support DMA or interrupts however, only register I/O (Read/Write node) and it is a lot slower than communicating from a Windows VI to your R series card.

Look for more information on programming and working with CompactRIO for more infromation.

[9845567540]

Thanks for the information. it is a lot helpful. My application demands are quite simple.

(i) I need to transfer 2 MB (max) of data to memory on the SbRIO that both the Host as well as the FPGA can access (Read and write). The FPGA will use this data during execution.

(ii) I also need to download the lv bit file and start/stop execution of fpga from Host.

How should i design my application for this scenario?

VJ

[VincentY]

Hi Christian

I have a big problem now.

My host Windows VI interacts directly to the FPGA VI on sbRIO 9602 without RT VI.

FPGA VI insert large amounts of data (180k Sample/sec) to FIFO.

I already enlarge the windows FIFO size to maximum.

Sometimes the execution time of FPGA READ FIFO VI on Windows is too long(about 1 ~2 sec), so the FIFO is overflow.

Coule you please provide some solutions?

Thanks!

Vincent Yang