Overflow problem

[euqinom2727]

Hii. I'm trying to acquire the data from a NI9223 module but I'm getting an overflow problem.

I believe the overflow would happen anyway, because I'm trying to acquire data at 50kHz on FPGA and I think the host VI it's not able to read the data in this rate, but what is strange is that the "FIFO Real" and "FIFO Imag" overflows before the "FIFO Signal" and I'm not even reading FIFO Signal. And I thought that the FFT would write on the FIFO just when it gets 256 data points, so it would write after the writing in the FIFO signal that occurs at the whole time, so the FIFO signal would always have more data points then the other ones, but this is not occuring. I think I missunderstood something or something is a bit off.

I've done my code in a way I can have more dynamic, sometimes reading 1 channels and others 4. It's in attachment.

If you could help me I would be so grateful

[ZYOng]

What is the Loop Rate of your Host VI?

You should move your TDMS logging to another loop using Producer/Consumer

[euqinom2727]

Based on this subVI "loop frequency" is super slow, it's like 10Hz

[ZYOng]

Assuming that the FPGA loop is indeed running at 50kHz, you are reading around 40k data from the FIFO each time. At the loop rate of 10Hz, the program should be reading fast enough to not overflow the FIFO buffer.

I would still recommend you separate the TDMS logging into a separate loop using Producer/Consumer architecture. This allows the CPU to process multiple loops simultaneously using multiple cores. Check the loop rates for each loop again.