I am trying to share time values and analogue data measued via cRIO FPGA to my VBAI2015 program. My highest capture rate is 19 Hz, therefore to ensure safetey of every measured data point I am using RT FIFOs (picture 1).
When the measurement starts, it should share a image number of 1 and a timestamt of 0 (ms) which works fine for measurements below 11 Hz. When going faster, it seems that the FPGA already writes the second values to the FIFO, before the vision builder program can read the first values. Since we are using FIFOs (size 50 each), it should not make a difference. But when I first come to my read network variables and log data to csv, the first values written to the csv are clearely the ones from the second measurement (with 0.06 s time between measurement, time should be logged as 0, 0.06, 0.12, ...., but the first row (image number 1, time = 0 s) is missung, instead we get a image number = 2, time = 0.06 s. You can see the sequence in picture 3.
We are sure, that the first variables are written and shared into the network, because if we read them before entering the in picture 3 shown sequency, we can read them. But given the features of a FIFO, it should not matter when I read the values, i should get the right values.
Therefore I am not sure, if the FIFOs are working as intended. I can also tick a "use buffering" box in VBAI 2015, which always gets unticked when switchung from the "configuration interface" to the "inspection interface" and back.
How can I make sure, the FIFOs are working properly? Thank you!
