cRio DSP48 "overload"

[Markanbl]

Hello, 

I've been developing a control for a simulation using sbRio and it ran smoothly until we burned the sbRio or at least it's Ethernet port. Afterwards we switched to cRio and now we're unable to compile the VI as too much resources is used, namely DPS48. Currently it's at around 130% of its capacity. Of course, LabView gives us suggestions how to improve performance, we've tried couple of stuff but it still doesn't work. It's a mystery to me why it ran without problems on sbRio and it won't run on cRio as one of the guys in the lab is expert on LabView and Rio applications and he told me that the cRio is more powerful, at least the one we're using. Do you have any idea how to solve the problem without changing the code? It's not a big application, it's used to measure a voltage input and to control a virtual load and power output. At least it seems to me that it's not a big application and that it should run without problems on the cRio as I've seen the guys in the lab doing much more complex applications using the same cRio. 

I would be very grateful with any help you can provide. I've already found that there is a patch for similar problem...

http://digital.ni.com/public.nsf/allkb/8A46A432EA47D261862577B300779F41

Thank you in advance!

[sarahbl]

Hello Markanbl,

What type of cRIO do you use ? On witch sbRIO did you develop your code ? Which mode do you use, scan mode or FPGA Interface ?

Whithout these informations we can not help you. This is a very strange behavior.

Regards,

Sarah

[mdordai]

cRio-9024

sbRio-9636 and using FPGA Interface mode.

Thank you,

Marko

[sarahbl]

I want to verify how many slices are contained within the FPGA chip in the sbRIO abd in the sbRIO. For the sbRIO you can find the informations in this KB.

But for the 9024, the FPGA is in the backplane, so I need to know which nackplane you are using with your cRIO.

Thanks,

Sarah