user defined variable FPGA read time / max loop rate

[MarkCG]

Does anyone have any idea on what kind of time it takes to read / write to a user defined IO variable in FPGA? Is it similar to what you would get with register I/O items or local variables? 

[Catherine-B]

Hi MarkCG,

I have not seen benchmarks specifically for reading from/writing to user defined variables. I would expect it to be in the same ballpark as reading/writing local variables.

[MrQuestion]

Your question is fairly vague. 

There are many variables to this.

One, What is your end point of reading? Are you reading the user defined IO on you client (PC) as you would with something like NI Scan Engine and select FPGA add on cards? Or are you talking about reading a value in your FPGA code?

Also what type of user defined IO and on what hardware.

There are some hardware cards that uses a parallel to serial conversion on the DIO to help save pin count going to the FPGA. If you have hardware like this, then it may take several clock pulses to clock the data from the converter, and then the IP hidden in the background will break this down into a nifty value for you to read as your defined IO.

If you are doing a straight read of a port  many cards will have sometype of buffer on them to protect the FPGA. So when you sample your data you may be a clock cycle behind the actual data.

You will also have factors such as SCTL or the lazy while loop. The SCTL is much more predictable in timing (obviously). The lazy while loop is a safer design practice for less experineced FPGA programmers, but will add in tons of buffers (flip/flops) to the data stream. Making it much harder to predict timing. 

[MarkCG]

Hi all,

to answer Mr.Questions question, I am talking about reading a Host-to-FPGA configured user defined I/O variables in my FPGA code, as well as writing FPGA-to-Host configured User IOVs, also in FPGA code. 

Specifically I am discussing this within context of a cRIO-9144 chassis running custom FPGA code. I am actually reading and writing to the user IOVs inside a simple (not timed) while loop.

It would nice if there was more info out there on the IP that's working in the background you mentioned. It would be nice to have info on approximate propagation time/ execution time for functions, which I realize of course will be different for each target.  

I took CatherineB's suggestion and treated them as if they where register items--- I was able to have my loop iterate to 5 kHz , but did not push it higher since I don't need to that high. 

I am also somewhat curious as to how the user IO variables affect jitter-- what happens when the IOV data gets pushed out to the network? Does that make a shared resource that has to have arbitration? 

Regards,

Mark Garnett

[Jesse_D]

Hey Mark, 

This question doesn't make a lot of sense to me if you are using a 9144 and not a 9148. Unless you are worried about closing timing on the FGPA or the effect the delay will have on your FPGA code you shouldn't need to worry about this. 

Instead you can monitor the VPI and VPO points on the FPGA, explained in the help. Anything written from the chassis before the VPI should be read on that cycle, and vice versa. 

Also, the Ethercat protocol guarantees that the creation of IOVs will not affect jitter.