I am having USRP X300 device with following tool versions: Vivado 2021.1 - AR76780n, GNU radio version - v3.11.0.0git-820-g2adbd4ea UHD version - UHD_4.7.0.0-84-gbdada1ed I have created FPGA image file for HG mode using "rfnoc_image_builder". It includes radio0/1, DDC0/1, DUC0/1 and replay module by default. I tested it on hardware also. It works fine. Now I want to add different RFNoC block in my design. On following "https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0" guide, I am trying to add FFT IP. This gives multi-driven clock error in implementation. Is it because this guide is for X310 board. Can anyone guide me the process of editing of ".yml script "to add FFT block for USRP X300. Another question is about register map. Can anyone explain where can I find refister map for USRP X300 Thanks and regards, Chhavi

USRP Software Radio

I am having USRP X300 device with following tool versions:

Vivado 2021.1 - AR76780n,

GNU radio version - v3.11.0.0git-820-g2adbd4ea

UHD version - UHD_4.7.0.0-84-gbdada1ed

I have created FPGA image file for HG mode using "rfnoc_image_builder". It includes radio0/1, DDC0/1, DUC0/1 and replay module by default. I tested it on hardware also. It works fine. Now I want to add different RFNoC block in my design. On following "https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0" guide, I am trying to add FFT IP. This gives multi-driven clock error in implementation. Is it because this guide is for X310 board. Can anyone guide me the process of editing of ".yml script "to add FFT block for USRP X300.
Another question is about register map. Can anyone explain where can I find refister map for USRP X300

Thanks and regards,

Chhavi